ISTQB CT-AuT study materials
ISTQB CT-AuT study resources

ISTQB CT-AuT key terms

ISTQB CT-AuT · Get comfortable with the vocabulary.

Automotive SPICE® (ASPICE)

A process assessment model derived from ISO/IEC 33000 used by the automotive industry to rate supplier development processes from level 0 to level 5, with separate process groups for system, software and hardware engineering plus supporting processes.

Related: Capability Level, Process Attribute, Traceability
Capability Level

A rating on the six-point scale (0 to 5) describing how well a process performs and how consistently it is institutionalized, determined by the extent to which its process attributes are achieved.

Related: Automotive SPICE® (ASPICE), Process Attribute
Process Attribute

A measurable characteristic of process capability, such as performance management or process definition, whose achievement rating (N, P, L, F) determines whether a capability level is reached.

Related: Capability Level, Automotive SPICE® (ASPICE)
Bidirectional Traceability

The ability to follow a requirement forward to its design, implementation and test cases and backward from any test or code element to the originating requirement, enabling impact analysis and completeness checks during assessments.

Related: Automotive SPICE® (ASPICE), Requirements-Based Testing
ISO 26262

The functional safety standard for road vehicles covering the lifecycle from concept through decommissioning, defining hazard analysis, safety goals, ASILs, safety mechanisms and confirmation measures for electrical/electronic systems.

Related: ASIL, Safety Goal, Safety Mechanism
ASIL (Automotive Safety Integrity Level)

A risk classification from A (lowest) to D (highest) assigned to safety goals based on severity, probability of exposure and controllability, determining the rigour of required development and verification activities.

Related: Safety Goal, ISO 26262, Freedom from Interference
Safety Goal

A top-level safety requirement derived from hazard analysis and risk assessment that states what must be achieved to avoid an unreasonable level of risk, without prescribing a technical solution.

Related: ASIL (Automotive Safety Integrity Level), Hazard Analysis and Risk Assessment (HARA)
Hazard Analysis and Risk Assessment (HARA)

The ISO 26262 activity that identifies hazardous events at the vehicle level and assigns severity, exposure and controllability ratings in order to determine safety goals and their ASILs.

Related: Safety Goal, ASIL (Automotive Safety Integrity Level)
Safety Mechanism

A technical measure implemented in hardware or software, such as a plausibility check, watchdog or redundant channel, that prevents a fault from leading to a violation of a safety goal or brings the system to a safe state.

Related: Freedom from Interference, Safe State, ISO 26262
Safe State

An operating mode of the system in which risk is acceptably low, for example degraded torque or a controlled shutdown, that the system reaches or maintains when a fault is detected.

Related: Safety Mechanism, Fault Detection
Freedom from Interference

The property that a lower-ASIL or non-safety function cannot corrupt the output of a higher-ASIL function, demonstrated through criteria such as memory partitioning, timing and communication protection.

Related: ASIL (Automotive Safety Integrity Level), Safety Mechanism
Fault Detection

The process by which a system or test observes deviations from specified behaviour, such as out-of-range sensor values or checksum mismatches, and reports them so that fault reactions can be triggered.

Related: Safe State, Safety Mechanism
AUTOSAR Classic Platform

A standardized layered software architecture for deeply embedded, hard real-time ECUs comprising basic software, runtime environment and application software components with statically configured communication.

Related: Software Component (SWC), Runtime Environment (RTE), Basic Software (BSW)
Software Component (SWC)

An encapsulated AUTOSAR application unit that provides and requires ports and communicates only through the runtime environment, allowing it to be tested and deployed independently of the ECU it later resides on.

Related: Runtime Environment (RTE), Virtual Function Bus (VFB), AUTOSAR Classic Platform
Runtime Environment (RTE)

The AUTOSAR middleware layer that implements the virtual function bus on a concrete ECU, routing inter-component communication and runnables to basic software services.

Related: Software Component (SWC), Virtual Function Bus (VFB)
Virtual Function Bus (VFB)

An abstract communication concept in AUTOSAR through which software components exchange data and operations without knowing whether the partner resides on the same ECU or another one.

Related: Software Component (SWC), Runtime Environment (RTE)
Basic Software (BSW)

The standardized AUTOSAR layer providing operating system, communication, memory, diagnostic and I/O services to application software, configured through modules such as the ECU abstraction and services layers.

Related: AUTOSAR Classic Platform, Runtime Environment (RTE)
Software-in-the-Loop (SiL)

A test environment in which production or generated application code runs as compiled software on a host PC, with the plant and bus environment simulated, enabling early automated and scalable testing without ECU hardware.

Related: Model-in-the-Loop (MiL), Hardware-in-the-Loop (HiL), XiL
Model-in-the-Loop (MiL)

A test environment in which controller and plant are both executable models, typically in a modelling tool, used to validate control algorithms and requirements before code generation.

Related: Software-in-the-Loop (SiL), XiL
Hardware-in-the-Loop (HiL)

A test environment in which a real ECU or network of ECUs is connected to a real-time simulated plant and vehicle environment, allowing electrical faults, sensor signals and bus traffic to be injected safely.

Related: Software-in-the-Loop (SiL), XiL, Restbus Simulation
XiL

An umbrella term for the family of in-the-loop test configurations (MiL, SiL, PiL, HiL) that differ in which parts are real and which are simulated, chosen according to test objective and maturity.

Related: Model-in-the-Loop (MiL), Software-in-the-Loop (SiL), Hardware-in-the-Loop (HiL)
Restbus Simulation

The simulation of all communication partners on a vehicle network so that the device under test receives realistic periodic frames and can transmit without real ECUs being present.

Related: Hardware-in-the-Loop (HiL), Bus Simulation
Real-Time Simulation

Execution of plant models with guaranteed timing so that simulated signals are produced within fixed cycle times, matching the physical dynamics the ECU expects from the real vehicle.

Related: Hardware-in-the-Loop (HiL), Bus Simulation
Bus Simulation

The generation and monitoring of vehicle network traffic (CAN, LIN, FlexRay, Automotive Ethernet) in a test environment, including frame scheduling, signal manipulation and fault injection on the bus.

Related: Restbus Simulation, Real-Time Simulation
Back-to-Back Testing

Comparing outputs of two versions of a system, such as a model and its generated code, with identical inputs to detect behavioural differences introduced by transformation or optimization.

Related: Model-in-the-Loop (MiL), Software-in-the-Loop (SiL)
Static Analysis

Examination of source code or models without executing them, using tools or reviews to find violations of coding rules, suspicious constructs, complexity hotspots and potential runtime faults.

Related: MISRA C, Coding Guideline, Code Review
MISRA C

A widely applied set of coding guidelines for the C language that restricts error-prone constructs to improve safety, portability and analysability of embedded automotive software.

Related: Static Analysis, Coding Guideline, Rule Deviation
Coding Guideline

A documented set of rules and recommendations for writing source code, such as naming, complexity limits and forbidden language features, checked automatically and enforced through reviews.

Related: MISRA C, Static Analysis
Rule Deviation

A formally justified and approved exception to a coding rule, recorded with rationale and risk assessment, so that an intentional violation does not invalidate the static analysis result.

Related: Coding Guideline, MISRA C
Code Review

A systematic examination of source code by people, guided by checklists or the coding guideline, to find defects that tools miss, such as wrong algorithms, missing checks or unclear intent.

Related: Static Analysis, Coding Guideline
Control Flow Analysis

A static technique that builds the graph of possible execution paths through a program to detect unreachable code, missing returns, endless loops and to support structural coverage planning.

Related: Data Flow Analysis, Cyclomatic Complexity
Data Flow Analysis

A static technique tracking where variables are defined and where those definitions are used, revealing anomalies such as use before definition or definitions never used.

Related: Control Flow Analysis, Static Analysis
Cyclomatic Complexity

A count of the linearly independent paths through a piece of code, derived from the control flow graph, used to judge testability and to set a minimum number of structural test cases.

Related: Control Flow Analysis, Statement Coverage
Requirements-Based Testing

A dynamic test design approach in which test cases are derived from specified requirements and their acceptance criteria, aiming to show that each requirement is met and traceably verified.

Related: Bidirectional Traceability, Equivalence Partitioning
Equivalence Partitioning

A black-box technique that divides input and output ranges into classes expected to be processed the same way, so that one representative value per class is tested.

Related: Boundary Value Analysis, Requirements-Based Testing
Boundary Value Analysis

A black-box technique that selects test values at and around the edges of equivalence partitions, where defects in comparisons and limits most often occur.

Related: Equivalence Partitioning, Requirements-Based Testing
Statement Coverage

A structural coverage measure reporting the percentage of executable statements exercised by a test suite, used as an entry criterion for code-level testing in safety-related projects.

Related: Branch Coverage, Cyclomatic Complexity
Branch Coverage

A structural coverage measure reporting the percentage of decision outcomes (true and false of each branch) exercised, stronger than statement coverage and commonly required for higher ASILs.

Related: Statement Coverage, MC/DC
MC/DC (Modified Condition/Decision Coverage)

A structural coverage criterion requiring that each elementary condition in a decision is shown to independently affect the decision outcome, while every entry and exit point and every condition is exercised.

Related: Branch Coverage, ASIL (Automotive Safety Integrity Level)
Fault Injection

The deliberate introduction of errors such as corrupted signals, stuck bits, lost frames or short circuits during a test to verify that detection and safety mechanisms react as specified.

Related: Safety Mechanism, Hardware-in-the-Loop (HiL)