Engineer Electronics study materials
Engineer Electronics study resources

Engineer Electronics cheat sheet

Engineer Electronics · Keep the key ideas within reach.

Quick reference

Electronic Circuits and Devices

  • Diode equation: I = I_S (e^{V/(nV_T)} − 1), with V_T ≈ 26 mV at 300 K; n ≈ 1 for Ge, ≈ 2 for Si at low currents.

  • BJT active-region relations: I_C = β I_B, I_E = (β+1) I_B, I_C = I_S e^{V_BE/V_T}; base-emitter drop ≈ 0.7 V for Si in forward active.

  • MOSFET saturation: I_D = ½ k_n' (W/L)(V_GS − V_T)^2 (1 + λV_DS); triode: I_D = k_n' (W/L)[(V_GS − V_T)V_DS − V_DS²/2].

  • Small-signal BJT: g_m = I_C/V_T, r_π = β/g_m, r_o = V_A/I_C; MOSFET: g_m = √(2k_n'(W/L)I_D), r_o = 1/(λI_D).

  • Thermal voltage V_T = kT/q ≈ 25.9 mV at 300 K; diode forward drop decreases ≈ 2 mV/°C for constant current.

  • Zener regulation: series resistor R_S = (V_in − V_Z)/(I_Z + I_L); Zener must stay in breakdown between I_ZK and I_ZM.

  • Load-line method: DC load line V_CE = V_CC − I_C R_C; Q-point at intersection with device characteristic; compliance limits clipping.

  • Hybrid-π input resistance r_in = R_B ∥ r_π; voltage gain A_v = −g_m (R_C ∥ r_o) for common-emitter with bypassed emitter.

Quick reference

Analog Electronics

  • Ideal op-amp: infinite open-loop gain, infinite input impedance, zero output impedance; virtual short V+ = V− when negative feedback is present.

  • Inverting amplifier gain = −R_f/R_in; non-inverting gain = 1 + R_f/R_g; integrator V_o = −(1/RC)∫V_i dt; differentiator V_o = −RC dV_i/dt.

  • Slew rate limits full-power bandwidth: f_max = SR/(2π V_peak); op-amp GBW sets closed-loop bandwidth ≈ GBW/|A_cl| for dominant-pole compensation.

  • Barkhausen criterion for oscillation: loop gain magnitude = 1 and phase shift = 0° (or 360°) at the oscillation frequency.

  • Class B push-pull efficiency max = π/4 ≈ 78.5%; Class A max = 25% (resistive load) or 50% (transformer-coupled).

  • Instrumentation amplifier CMRR set by resistor matching; three-op-amp topology gives high input impedance and gain = (1 + 2R/R_g)(R_3/R_2).

  • Active filter Sallen-Key: ω_0 = 1/√(R_1R_2C_1C_2), Q = √(R_1R_2C_1C_2)/(C_2(R_1+R_2)) for unity-gain low-pass.

  • Noise: resistor thermal noise v_n = √(4kTRB); op-amp input noise combines voltage and current noise; SNR improves with narrower bandwidth.

Quick reference

Digital Electronics and Logic Design

  • Boolean identities: A + A'B = A + B; A + AB = A; De Morgan: (AB)' = A' + B', (A+B)' = A'B'.

  • Karnaugh map grouping: groups of 1, 2, 4, 8 adjacent cells; each group eliminates log2(size) variables; don't-cares may be included to enlarge groups.

  • Setup time t_su: data must be stable before active clock edge; hold time t_h: data must remain stable after edge; violation causes metastability.

  • Flip-flop timing: f_max = 1/(t_cq + t_comb + t_su); hold constraint: t_cq + t_comb,min ≥ t_h.

  • CMOS static power ≈ 0; dynamic power P = α C V_DD² f, where α is activity factor; short-circuit power adds during transitions.

  • Number systems: 2's complement range for n bits = −2^{n−1} to 2^{n−1}−1; overflow when carry into and out of MSB differ.

  • Universal gates: NAND and NOR each can implement any Boolean function; SR latch built from cross-coupled NAND or NOR gates.

  • Finite-state machine design: state diagram → state table → state assignment → next-state and output logic → flip-flop implementation.

Quick reference

Signals, Systems, and Communications

  • Nyquist–Shannon sampling theorem: sample at f_s > 2 f_max to avoid aliasing; reconstruction filter cutoff at f_s/2.

  • Fourier transform pairs: rect(t/τ) ↔ τ sinc(πfτ); δ(t) ↔ 1; e^{j2πf_0t} ↔ δ(f − f_0); convolution in time ↔ multiplication in frequency.

  • LTI system output y(t) = x(t) * h(t); frequency response H(f) = F{h(t)}; stability requires all poles in left half-plane (continuous) or inside unit circle (discrete).

  • Laplace transform: L{e^{−at}u(t)} = 1/(s+a); final-value theorem lim_{t→∞} f(t) = lim_{s→0} sF(s) if poles of sF(s) in LHP.

  • AM: bandwidth = 2 f_m; modulation index μ = A_m/A_c; overmodulation for μ > 1 causes envelope distortion.

  • FM: Carson's rule B ≈ 2(Δf + f_m); modulation index β = Δf/f_m; FM trades bandwidth for SNR improvement.

  • Shannon capacity C = B log2(1 + S/N); channel capacity in bits per second; SNR in linear power ratio.

  • PCM: quantization SNR ≈ 6.02 n + 1.76 dB for n-bit uniform quantizer with full-scale sine input; bit rate = n f_s.

Quick reference

Electromagnetic Fields and Waves

  • Maxwell's equations (time-harmonic, source-free): ∇×E = −jωμH, ∇×H = jωεE, ∇·D = 0, ∇·B = 0.

  • Wave impedance of free space η_0 = √(μ_0/ε_0) ≈ 377 Ω; intrinsic impedance η = √(μ/ε).

  • Phase velocity v_p = 1/√(με) = ω/β; wavelength λ = v_p/f = 2π/β.

  • Transmission line: characteristic impedance Z_0 = √(L/C); reflection coefficient Γ = (Z_L − Z_0)/(Z_L + Z_0); VSWR = (1+|Γ|)/(1−|Γ|).

  • Smith chart: normalized impedance z = Z/Z_0; full wavelength = 360° rotation; quarter-wave transformer matches Z_0 = √(Z_in Z_L).

  • Poynting vector S = E × H (W/m²); average power density for plane wave = |E|²/(2η).

  • Boundary conditions: tangential E continuous; tangential H continuous unless surface current; normal D continuous unless surface charge.

  • Skin depth δ = √(2/(ωμσ)); conductor attenuation increases with √f; good conductor condition σ ≫ ωε.

Quick reference

Power Electronics and Electrical Machines

  • Buck converter: V_o = D V_in; boost: V_o = V_in/(1−D); buck-boost: V_o = −V_in D/(1−D); CCM assumed.

  • Inductor ripple current ΔI_L = V_o(1−D)/(L f_s) for buck; choose L so ΔI_L < 20–40% of I_o typically.

  • Thyristor (SCR) latches on gate pulse and turns off when anode current falls below holding current I_H; di/dt and dv/dt limits require snubbers.

  • Three-phase induction motor synchronous speed n_s = 120 f/P (rpm); slip s = (n_s − n_r)/n_s; rotor frequency f_r = s f.

  • Transformer EMF equation E = 4.44 f N Φ_max; volt-per-turn rating sets core area and frequency scaling.

  • DC machine: E_a = K Φ ω; torque T = K Φ I_a; separately excited speed control via armature voltage or field weakening.

  • PWM inverter: fundamental output amplitude proportional to modulation index m_a; overmodulation reduces linearity; dead time prevents shoot-through.

  • Power factor correction: boost PFC shapes input current sinusoidal; displacement factor cos φ and distortion factor combine to true PF.

Quick reference

Control Systems and Instrumentation

  • Second-order system: ω_n natural frequency, ζ damping ratio; percent overshoot = 100 e^{−πζ/√(1−ζ²)}; settling time ≈ 4/(ζω_n) for 2% band.

  • Routh–Hurwitz array: number of sign changes in first column equals number of right-half-plane poles; zero row requires auxiliary polynomial derivative.

  • Steady-state error: type 0 step error 1/(1+K_p); type 1 ramp error 1/K_v; type 2 parabolic error 1/K_a.

  • Bode stability: gain crossover where |G| = 0 dB; phase margin = 180° + ∠G at gain crossover; gain margin = −20 log|G| at phase crossover.

  • PID controller: u(t) = K_p e + K_i ∫e dt + K_d de/dt; integral removes steady-state error; derivative adds damping but amplifies noise.

  • Instrumentation: Wheatstone bridge balance R_1/R_2 = R_3/R_4; strain gauge gauge factor GF = (ΔR/R)/ε.

  • Thermocouple Seebeck effect: V = S ΔT; cold-junction compensation required; RTD resistance approximately linear with temperature.

  • Sampling and quantization: ADC resolution = V_FS/2^n; SNR ≈ 6.02 n + 1.76 dB; anti-alias filter before ADC.

Quick reference

Microprocessors and Embedded Systems

  • ARM Cortex-M: 32-bit RISC, Thumb-2 instruction set, NVIC nested interrupts, memory-mapped peripherals; stack grows downward.

  • Interrupt latency: time from interrupt request to first instruction of ISR; reduced by tail-chaining and late arrival in NVIC.

  • Memory hierarchy: registers → cache → SRAM → flash → external; cache coherency needed with DMA; volatile keyword prevents compiler optimization.

  • UART: asynchronous, start/stop bits, baud rate = f_clk/(16 × divisor) for typical oversampling; RS-232 uses ±12 V levels.

  • I²C: two-wire (SDA, SCL), 7-bit addressing, open-drain with pull-ups; SPI: four-wire full-duplex, no addressing, higher throughput.

  • PWM generation: timer compare match sets duty cycle; frequency = f_timer/(prescaler × (ARR+1)); dead-band insertion for motor drives.

  • Watchdog timer resets MCU if not serviced within timeout; independent watchdog uses separate clock source for reliability.

  • Endianness: little-endian stores least significant byte at lowest address; ARM Cortex-M supports configurable endianness but typically little-endian.

Quick reference

Engineering Mathematics and Numerical Methods

  • Matrix: determinant of 2×2 [[a,b],[c,d]] = ad − bc; inverse exists if det ≠ 0; eigenvalues solve det(A − λI) = 0.

  • Newton–Raphson iteration x_{n+1} = x_n − f(x_n)/f'(x_n); quadratic convergence near simple root; fails if f' = 0.

  • Trapezoidal rule error ≈ −(b−a)³ f''(ξ)/12; Simpson's 1/3 rule error ≈ −(b−a)⁵ f⁽⁴⁾(ξ)/180 and requires even number of intervals.

  • Runge–Kutta 4th order: k_1 = h f(t_n, y_n), k_2 = h f(t_n + h/2, y_n + k_1/2), etc.; local error O(h⁵), global O(h⁴).

  • Laplace transform: L{f'} = sF(s) − f(0); L{sin ωt} = ω/(s² + ω²); convolution theorem L{f*g} = F(s)G(s).

  • Probability: Bayes P(A|B) = P(B|A)P(A)/P(B); mean of binomial np, variance np(1−p); Poisson mean = variance = λ.

  • Fourier series: f(t) = a_0/2 + Σ [a_n cos(nω_0t) + b_n sin(nω_0t)]; coefficients from integrals over one period.

  • Numerical differentiation central difference f'(x) ≈ [f(x+h) − f(x−h)]/(2h); error O(h²).