CPN CPE Computer Engineering key terms

A condition that prevents an instruction from executing in its planned pipeline slot. Data hazards arise from operand dependence, control hazards from branches, and structural hazards from two operations needing the same hardware resource simultaneously.

A technique that routes a result directly from a later pipeline stage back to an earlier stage that needs it, avoiding a stall. It resolves many read-after-write data hazards without waiting for the value to be written to the register file.

A deliberate pause inserted into instruction issue so that a dependent instruction waits until its operand is available. Stalls cost cycles; forwarding and scheduling reduce how often they are needed.

Hardware or compiler logic that guesses whether a branch is taken, and often its target, before the condition is resolved. A correct guess keeps the pipeline full; a misprediction flushes fetched instructions and wastes cycles.

Running instructions along a predicted path before knowing whether that path is correct, then committing results only if the guess holds. It improves throughput but creates security exposure when speculation leaves observable traces.

A protocol that keeps multiple private caches in a multiprocessor system consistent, so no core reads a stale copy of a shared location. Snooping and directory schemes are the common approaches.

The rules defining the order in which memory operations from different threads may appear to execute. It constrains what reordering hardware and compilers may perform and determines which synchronization primitives are required for correctness.

A cache organization in which each memory block maps to exactly one cache line, selected by index bits of the address. It is simple and fast but suffers conflict misses when blocks compete for the same line.

A cache organization in which each memory block may occupy any of several ways within one indexed set. Higher associativity reduces conflict misses at the cost of more comparators and slower lookup.

Two design philosophies. RISC favors simple fixed-length instructions and heavy register use; CISC favors richer variable-length instructions that do more per instruction. Modern processors blend features of both.

The degree to which independent instructions in a program can execute simultaneously. Superscalar issue, out-of-order execution, and deep pipelines increase it; true data dependences limit it.

A grid layout of a truth table arranged in Gray-code order so adjacent cells differ by one variable. Grouping adjacent 1s yields a minimized sum-of-products Boolean expression.

The process of reducing a logic expression to fewer terms or literals while preserving its truth table. Algebraic identities, Karnaugh maps, and Quine-McCluskey are standard methods.

An input combination whose output value is irrelevant because it never occurs or its result does not matter. Treating such entries as either 0 or 1 can simplify the resulting logic.

Setup time is how long data must be stable before a clock edge; hold time is how long it must remain stable after. Violating either causes metastability in a flip-flop.

A flip-flop state in which the output hovers between logic levels for an unpredictable time because setup or hold requirements were violated. It is mitigated by synchronizers, not eliminated by them.

Passing data between circuits clocked by unrelated clocks. Reliable designs use synchronizer flip-flops, asynchronous FIFOs, or handshake protocols to avoid metastability and data loss.

A design-time check that computes worst-case path delays against clock constraints without simulation vectors. It reports setup and hold violations and the maximum achievable clock frequency.

The longest delay path through a combinational logic network between registers. It sets the minimum clock period for the circuit, so shortening it raises maximum operating frequency.

Two finite-state machine styles. A Moore machine's outputs depend only on the current state; a Mealy machine's outputs depend on state and current input, typically responding faster but glitchier.

Specifying a sequential circuit as states, transitions, inputs, and outputs, then encoding states and deriving next-state and output logic. It is the standard method for control logic.

A set of processes each waiting for a resource held by another in the set, so none can proceed. It requires mutual exclusion, hold-and-wait, no preemption, and circular wait to occur.

A synchronization primitive holding an integer count with atomic wait and signal operations. A binary semaphore acts as a mutex; a counting semaphore limits access to a pool of resources.

A high-priority task is blocked because a low-priority task holds a needed lock and is itself preempted by a medium-priority task. Priority inheritance or ceiling protocols bound the delay.

An address translation scheme mapping virtual pages to physical frames via per-process page tables. It provides isolation, demand paging, and a larger apparent address space than physical RAM.

A small associative cache of recent virtual-to-physical address translations. A TLB hit avoids walking the page table; a miss adds latency and may require several memory accesses.

A condition where the working set of running processes exceeds available physical memory, so the system spends most time servicing page faults instead of executing instructions.

Connection setup using SYN, SYN-ACK, and ACK segments to agree on initial sequence numbers and confirm both directions are reachable. It precedes reliable data transfer.

Sender-side algorithms (slow start, congestion avoidance, fast retransmit and recovery) that adapt the sending rate to inferred network capacity, reducing loss and collapse.

Dividing an IP address space into smaller networks using prefix lengths, expressed as address/prefix. CIDR allows variable-length prefixes and route aggregation, replacing classful addressing.

ARP resolves an IP address to a link-layer MAC address on a local segment; routers forward packets between subnets using routing tables. Together they deliver packets hop by hop.

Progressively removing redundancy and update anomalies: atomic values (1NF), no partial dependency on part of a key (2NF), no transitive dependency on non-key attributes (3NF).

Atomicity, consistency, isolation, and durability: the guarantees a transactional database provides so that concurrent failures never leave partially applied or contradictory data.

A concurrency control protocol in which a transaction acquires all locks before releasing any, in growing and shrinking phases. It guarantees serializability but can cause deadlock.

An auxiliary structure, commonly a B-tree, that speeds lookups on indexed columns at the cost of extra storage and slower writes. It turns full scans into targeted searches.

A scheme using a mathematically linked key pair: a public key for encryption or verification and a private key for decryption or signing. Security rests on problems such as factoring or discrete logarithms.

A value produced by hashing a message and encrypting the hash with a private key, verifiable by anyone with the public key. It provides integrity, authentication, and non-repudiation.

A one-way function mapping arbitrary input to a fixed-length digest, with preimage and collision resistance. It underpins integrity checks, password storage, and signature schemes.

A hardware counter that resets the system if software fails to service it within a set interval. It recovers embedded systems from hangs and runaway code.

Policies guaranteeing deadlines: rate-monotonic assigns fixed priorities by period; earliest-deadline-first dynamically picks the task with the nearest deadline. EDF is optimal for preemptive uniprocessors.

The delay between an interrupt request and the start of its handler, including hardware recognition, context save, and any masked region. It bounds worst-case response time in real-time systems.