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CPN CPE Computer Engineering study materials
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CPN CPE Computer Engineering practice questions

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Question 1Computer Architecture and Organization

In a five-stage pipeline (IF, ID, EX, MEM, WB), a program executes 1000 instructions with no hazards and a clock of 1 ns. What is the approximate total execution time, ignoring pipeline fill?

  1. 1005 ns
  2. 1000 ns
  3. 1004 ns Correct answer.
  4. 5000 ns

Explanation

With no hazards, one instruction completes per cycle after the pipeline fills, so time is about (number of instructions + pipeline depth - 1) cycles. That gives 1000 + 5 - 1 = 1004 cycles at 1 ns each. The 1000 ns figure ignores pipeline fill entirely.

Question 2Computer Architecture and Organization

Which statement correctly describes the role of the program counter (PC) in a processor datapath?

  1. It stores the result of the most recent ALU operation.
  2. It records the number of instructions retired so far.
  3. It holds the address of the next instruction to be fetched. Correct answer.
  4. It caches recently accessed data words for reuse.

Explanation

The program counter is a register holding the address of the instruction to be fetched next, and it is updated each cycle (normally incremented, or overwritten by a branch target). It is not a data or result register.

Question 3Computer Architecture and Organization

A direct-mapped cache has 64 lines and a block size of 16 bytes. Which main-memory address maps to the same cache line as address 0x00A3?

  1. 0x00B3
  2. 0x01A3
  3. 0x04A3 Correct answer.
  4. 0x0FA3

Explanation

The block offset uses log2(16)=4 bits, and the line index uses log2(64)=6 bits, so the index is address bits 4 through 9. Two addresses share a line when they agree on those six bits, meaning they differ by a multiple of 64 lines times 16 bytes = 1024 bytes (0x400). 0x04A3 - 0x00A3 = 0x400, so they collide.

Question 4Computer Architecture and Organization

In a set-associative cache, what is the primary effect of increasing associativity while keeping total capacity and block size fixed?

  1. The block offset grows and compulsory misses fall.
  2. The number of index bits increases and conflict misses fall.
  3. The number of index bits decreases and conflict misses fall. Correct answer.
  4. The tag width shrinks and capacity misses fall.

Explanation

Higher associativity means fewer sets, so fewer address bits are used for the set index while more are used for the tag. Fewer sets with more ways reduces conflict misses, though capacity and compulsory misses are unaffected.

Question 5Computer Architecture and Organization

A benchmark runs in 10 s on a single core. If 60% of its execution time is perfectly parallelizable and the remainder is strictly serial, what is the best possible speedup on many cores according to Amdahl's law?

  1. 4.0
  2. 10.0
  3. 1.67
  4. 2.5 Correct answer.

Explanation

Amdahl's law bounds speedup by 1/(serial fraction). The serial fraction is 40%, so the maximum speedup as cores grow without limit is 1/0.4 = 2.5. Perfect parallelization of the other 60% cannot remove the serial portion.

Question 6Computer Architecture and Organization

Which hazard is eliminated by forwarding (bypassing) in a classic five-stage pipeline?

  1. A control hazard caused by a taken conditional branch.
  2. A structural hazard on a single unified memory port.
  3. A data hazard where a load result is needed by the immediately following instruction.
  4. A data hazard where an ALU result is needed by the immediately following instruction. Correct answer.

Explanation

Forwarding routes a result from the EX/MEM or MEM/WB pipeline register directly to the ALU input, removing the stall for an ALU-to-ALU dependency. A load-use dependency still needs one stall cycle because the loaded data is only available after MEM.

Question 7Computer Architecture and Organization

A two-way set-associative TLB has 32 total entries. How many sets does it contain?

  1. 16 Correct answer.
  2. 64
  3. 8
  4. 32

Explanation

The number of sets equals total entries divided by associativity, so 32 divided by 2 gives 16 sets. Each set holds two entries (the two ways).

Question 8Computer Architecture and Organization

Which cache write policy writes only to the cache on a store and defers main-memory update until the block is evicted?

  1. Write-allocate
  2. Non-temporal streaming
  3. Write-back Correct answer.
  4. Write-through

Explanation

A write-back cache marks a dirty block and updates main memory only when that block is replaced. This reduces memory traffic compared with write-through, which writes to memory on every store.

Question 9Computer Architecture and Organization

A system has a 4-entry fully associative TLB with LRU replacement. The page accesses are 1, 2, 3, 4, 1, 2, 5, 1, 2, 3. How many TLB misses occur, assuming the TLB starts empty?

  1. 4
  2. 5
  3. 6 Correct answer.
  4. 7

Explanation

The first four accesses (1,2,3,4) all miss and fill the TLB. Accesses 1 and 2 hit. Access 5 misses and evicts page 3 (least recently used), then 1 and 2 hit, and access 3 misses and evicts page 4. That totals 4 + 1 + 1 = 6 misses.

Question 10Computer Architecture and Organization

In a virtual memory system, what is the purpose of the dirty bit in a page table entry?

  1. It records the frequency of accesses for replacement decisions.
  2. It indicates the access permissions for user versus supervisor mode.
  3. It marks whether the page has been modified since it was loaded. Correct answer.
  4. It marks whether the page is currently present in physical memory.

Explanation

The dirty (modified) bit records that a page has been written since being brought into memory, so the operating system knows it must write the page back to disk before eviction. A clean page can simply be discarded.

Question 11Computer Architecture and Organization

Which statement best characterizes a RISC instruction set compared with a CISC instruction set?

  1. It provides complex addressing modes for arithmetic operations.
  2. It favors fixed-length instructions and load/store memory access. Correct answer.
  3. It uses many variable-length instructions with memory operands.
  4. It relies on microcode to sequence most instructions.

Explanation

RISC designs typically use fixed-length, simply decoded instructions with arithmetic operating only on registers, and memory accessed through explicit load and store instructions. This regularity simplifies pipelining.

Question 12Computer Architecture and Organization

A CPU has a 32-bit virtual address with 4 KB pages and a two-level page table where each level's table fits in one page. How many bits are used for each level's index?

  1. 10 Correct answer.
  2. 8
  3. 12
  4. 20

Explanation

With 4 KB pages, the page offset is 12 bits, leaving 20 bits for the virtual page number. A page-table page holds 4096/4 = 1024 entries of 4 bytes, needing 10 index bits per level, so two levels use 20 bits exactly.

Question 13Computer Architecture and Organization

Which statement about a superscalar processor is accurate?

  1. It relies on a very long pipeline rather than multiple issue units.
  2. It executes instructions strictly in program order with one issue slot.
  3. It executes only vector instructions across wide data lanes.
  4. It fetches and issues multiple independent instructions per cycle. Correct answer.

Explanation

A superscalar processor contains multiple issue units so it can fetch, decode, and dispatch more than one instruction per cycle, exploiting instruction-level parallelism. It typically requires dependency checking to preserve correctness.

Question 14Computer Architecture and Organization

In Tomasulo's algorithm, what is the function of the register status (or busy) table?

  1. It maps each register to the reservation station or unit that will produce it. Correct answer.
  2. It stores the branch history used for direction prediction.
  3. It holds the actual computed values of all architectural registers.
  4. It records the cache line replacement order for the data cache.

Explanation

The register status table tracks, for each architectural register, which reservation station will produce its pending value, enabling register renaming and out-of-order issue. Actual values live in the register file or forwarding paths, not in the status table.

Question 15Computer Architecture and Organization

A branch predictor uses a 2-bit saturating counter initialized to 'weakly not taken'. A loop branch is taken 9 times then not taken once, repeatedly. After the first full iteration, what prediction does the counter give on the loop's final (not-taken) occurrence?

  1. Taken, because the counter saturates at strongly taken.
  2. Not taken, because the initial state was not taken.
  3. Not taken, because the counter has already switched.
  4. Taken, because the counter is still in a taken state. Correct answer.

Explanation

Nine taken outcomes drive the 2-bit counter from weakly not taken through weakly taken to strongly taken, where it saturates. A single not-taken outcome only decrements it to weakly taken, so the final occurrence is still predicted taken and mispredicted.

Question 16Computer Architecture and Organization

Which memory hierarchy level is typically managed by hardware rather than by the operating system?

  1. The L1 data cache Correct answer.
  2. Disk swap space
  3. Main memory paging
  4. The file system buffer

Explanation

Caches such as L1 are managed transparently by hardware, which handles placement, replacement, and coherence without OS involvement. Paging, swap, and file buffering involve OS policy and software structures.

Question 17Computer Architecture and Organization

A disk has an average seek time of 5 ms, a rotational latency of 3 ms, and transfers 4 KB per access at 200 MB/s. What is the approximate average access time for a random 4 KB read?

  1. 11.0 ms
  2. 8.02 ms Correct answer.
  3. 5.02 ms
  4. 8.20 ms

Explanation

Average access time is seek plus rotational latency plus transfer time. Transfer time is 4 KB / 200 MB/s = 4096/200,000,000 s ≈ 0.02 ms, so total is 5 + 3 + 0.02 ≈ 8.02 ms.

Question 18Computer Architecture and Organization

Which statement correctly distinguishes RAID 1 from RAID 5?

  1. RAID 1 provides no redundancy; RAID 5 tolerates two disk failures.
  2. RAID 1 uses distributed parity; RAID 5 mirrors data across two disks.
  3. RAID 1 mirrors data; RAID 5 stripes data with distributed parity. Correct answer.
  4. RAID 1 stripes data with parity; RAID 5 mirrors every block.

Explanation

RAID 1 duplicates data across mirrored disks for redundancy, while RAID 5 stripes data and parity across at least three disks, tolerating one disk failure. Neither RAID 5 nor RAID 1 tolerates two simultaneous failures.

Question 19Computer Architecture and Organization

In the MESI cache coherence protocol, a block in the Modified state means which of the following?

  1. The block is clean and shared with other caches.
  2. The block is present but has not been validated yet.
  3. The block is dirty and this cache holds the only valid copy. Correct answer.
  4. The block is read-only and present in several caches.

Explanation

Modified means the local cache has written the block, so it is dirty and the only valid copy exists there; main memory is stale. Any other cache requesting it must obtain it from this cache or memory must be updated.

Question 20Computer Architecture and Organization

A snooping coherence protocol observes a read miss from another processor for a block this cache holds in Modified state. What must happen?

  1. The block is invalidated and the request is retried later.
  2. The modified block is supplied and written back or shared. Correct answer.
  3. The block is silently dropped without supplying data.
  4. The requesting processor must fetch stale data from memory.

Explanation

Because main memory may be stale when a block is Modified, the owning cache must supply the data to the requester and either write it back to memory or transition to a shared state. This preserves coherence.

Question 21Computer Architecture and Organization

What is the main advantage of a virtually indexed, physically tagged (VIPT) L1 cache over a physically indexed cache?

  1. It allows cache indexing to overlap with TLB lookup. Correct answer.
  2. It eliminates cache coherence traffic between cores.
  3. It removes the need for address translation entirely.
  4. It guarantees no cache aliasing can ever occur.

Explanation

In a VIPT cache, the set index comes from the virtual address so indexing can begin before translation completes, overlapping with the TLB lookup while the tag comparison still uses the physical address. This reduces hit latency without sacrificing correctness.

Question 22Computer Architecture and Organization

A system uses 16-bit instructions and a byte-addressable memory. The PC holds 0x0100 and the instruction at that address is a two-byte instruction. After fetching it in a simple machine without delay slots, what value does the PC hold?

  1. 0x0100
  2. 0x0101
  3. 0x0102 Correct answer.
  4. 0x0200

Explanation

With byte addressing and a two-byte instruction, the PC advances by two bytes, from 0x0100 to 0x0102. Advancing by one would be correct only for byte-sized instructions.

Question 23Computer Architecture and Organization

Which addressing mode computes the effective address as the contents of a base register plus a constant offset encoded in the instruction?

  1. PC-relative
  2. Immediate
  3. Base-plus-displacement Correct answer.
  4. Register indirect

Explanation

Base-plus-displacement addressing adds a signed displacement from the instruction to a base register to form the effective address, which is common for structure and array access. Register indirect uses only a register value, and immediate embeds the operand itself.

Question 24Computer Architecture and Organization

A processor's clock is raised from 2 GHz to 3 GHz, but the higher clock forces memory stalls that increase the average CPI from 1.5 to 2.0. What is the effect on execution time for a fixed instruction count?

  1. It decreases by about 11%. Correct answer.
  2. It increases by about 33%.
  3. It decreases by about 25%.
  4. It remains unchanged.

Explanation

Execution time equals instruction count times CPI divided by clock rate. The ratio of new to old time is (2.0/3.0)/(1.5/2.0) = 0.667/0.75 ≈ 0.889, so time falls by roughly 11%. The CPI increase partly offsets the frequency gain.

Question 25Digital Logic and Circuit Design

A 4-bit synchronous binary counter is clocked continuously. How many flip-flop output transitions (bit toggles) occur in total during one complete 16-state cycle?

  1. 15
  2. 30 Correct answer.
  3. 16
  4. 32

Explanation

In a binary up-counter, the LSB toggles every clock (16 toggles per cycle), the next bit every 2 clocks (8), then 4, then 2. Summing 16 + 8 + 4 + 2 gives 30 total bit transitions per full modulus-16 cycle.

Question 26Digital Logic and Circuit Design

Which logic family characteristic best explains why CMOS gates draw almost no static DC input current?

  1. Emitter-coupled differential pairs steer current away from the input
  2. Complementary MOS transistors present a high-impedance gate oxide to the driving stage Correct answer.
  3. Bipolar input transistors are biased in cutoff during steady state
  4. Schottky clamping diodes block reverse leakage at the input

Explanation

The gate of a MOSFET is separated from the channel by an insulating oxide, so the input looks like a small capacitance and only charging current flows during switching. Static current is limited to leakage, which is orders of magnitude below bipolar input currents.

Question 27Digital Logic and Circuit Design

A Karnaugh map for a four-variable function has ones at minterms 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 except that minterm 15 is a don't-care. What is the minimal sum-of-products form?

  1. A' + B' + C' + D'
  2. A + B + C + D
  3. A + B + C
  4. 1 (constant logic high) Correct answer.

Explanation

All sixteen minterms are either asserted or don't-care, so the function can be covered by a single group of sixteen cells. That group corresponds to the constant 1, which requires no literals at all.

Question 28Digital Logic and Circuit Design

In a Mealy finite-state machine, the output depends on which quantities?

  1. The next state and the clock phase
  2. The present state only
  3. Both the present state and the present input Correct answer.
  4. The present input only

Explanation

A Mealy machine computes its output combinationally from the current state register contents and the current primary inputs, so the output can change as soon as an input changes. A Moore machine, by contrast, depends on state alone.

Question 29Digital Logic and Circuit Design

A D flip-flop has setup time 2 ns, hold time 0.5 ns, and clock-to-Q delay 3 ns. A combinational path between two such registers has maximum delay 8 ns and minimum delay 1 ns. What is the minimum clock period for reliable operation?

  1. 10.5 ns
  2. 10 ns
  3. 11 ns
  4. 13 ns Correct answer.

Explanation

The setup constraint requires period >= clock-to-Q + combinational max + setup = 3 + 8 + 2 = 13 ns. The hold constraint (clock-to-Q + combinational min >= hold) is satisfied since 3 + 1 = 4 ns exceeds 0.5 ns, so the setup bound governs.

Question 30Digital Logic and Circuit Design

Which statement correctly describes the behavior of a JK flip-flop when both J and K are asserted during a clocked edge?

  1. The output is set to 1
  2. The output is reset to 0
  3. The output toggles to its complement Correct answer.
  4. The output holds its previous value

Explanation

The JK flip-flop is defined so that simultaneous J = K = 1 produces a toggle rather than the forbidden state of an SR latch. This toggling mode is what makes JK devices convenient for counter design.

Question 31Digital Logic and Circuit Design

A 3-to-8 binary decoder with active-low outputs is used to select memory banks. What output pattern appears when the 3-bit select input equals 101?

  1. Only output 5 is high; all others are low
  2. Only output 5 is low; all others are high Correct answer.
  3. Only output 2 is low; all others are high
  4. All outputs are low

Explanation

A binary decoder asserts exactly one output corresponding to the binary value on its select lines, so input 101 selects line 5. Because the outputs are active-low, the selected line is driven low while the unselected lines stay high.

Question 32Digital Logic and Circuit Design

A positive-edge-triggered D flip-flop is driving a load through a buffer. Which condition describes the hold-time requirement at the receiving register?

  1. Data must remain stable for a duration after the active clock edge arrives Correct answer.
  2. The clock must remain high for at least one propagation delay
  3. Data must be stable for a duration before the active clock edge arrives
  4. The clock-to-Q delay must exceed the combinational path delay

Explanation

Hold time is the interval after the capturing clock edge during which the data input must not change, ensuring the register captures the intended value. Setup time is the corresponding window before the edge.

Question 33Digital Logic and Circuit Design

What is the primary functional difference between a latch and a flip-flop in digital design?

  1. A latch stores analog values, while a flip-flop stores only digital values
  2. A latch is edge-triggered, while a flip-flop is level-sensitive
  3. A latch has no feedback path, while a flip-flop does
  4. A latch is level-sensitive, while a flip-flop is edge-triggered Correct answer.

Explanation

A latch is transparent for the entire duration its enable is asserted, so its output can follow the input. A flip-flop captures data only at a clock edge and holds it otherwise, giving cleaner timing behavior in synchronous systems.

Question 34Digital Logic and Circuit Design

A synchronous counter must produce the sequence 0, 2, 4, 6, 0, ... using three flip-flops. What is the modulus of this counter, and how many unused states exist?

  1. Modulus 8 with 0 unused states
  2. Modulus 4 with 2 unused states
  3. Modulus 6 with 2 unused states
  4. Modulus 4 with 4 unused states Correct answer.

Explanation

The sequence contains four distinct states (0, 2, 4, 6), so the modulus is 4. Three flip-flops can represent eight states, leaving four states (1, 3, 5, 7) that are never visited and must be handled to avoid lock-up.

Question 35Digital Logic and Circuit Design

Which representation of a signed binary number is used when the value is formed by inverting all bits of the magnitude and adding one?

  1. One's complement
  2. Offset binary
  3. Two's complement Correct answer.
  4. Sign-magnitude

Explanation

Two's complement forms the negative of a number by bitwise inversion followed by adding one, which gives a unique zero and simplifies arithmetic. Sign-magnitude and one's complement both have two representations of zero.

Question 36Digital Logic and Circuit Design

An 8-bit two's complement value 1111 0110 is interpreted as a signed decimal number. What is its value?

  1. -11
  2. -9
  3. -10 Correct answer.
  4. 246

Explanation

The leading bit is 1, so the value is negative. Inverting the bits gives 0000 1001 and adding one gives 0000 1010, which is 10, so the original number is -10.

Question 37Digital Logic and Circuit Design

A full adder is built from two half adders and an OR gate. If inputs A = 1, B = 1, and Cin = 1, what are the sum and carry-out outputs respectively?

  1. Sum 0, carry-out 1
  2. Sum 0, carry-out 0
  3. Sum 1, carry-out 0
  4. Sum 1, carry-out 1 Correct answer.

Explanation

The full adder computes the arithmetic sum A + B + Cin = 3, which in binary is 11. The least significant bit is the sum (1) and the upper bit is the carry-out (1).

Question 38Digital Logic and Circuit Design

Why is a carry-lookahead adder typically faster than a ripple-carry adder of the same width?

  1. It computes group generate and propagate signals to bypass serial carry propagation Correct answer.
  2. It operates on a higher supply voltage to reduce gate delays
  3. It eliminates the need for any carry signals between bit positions
  4. It uses fewer transistors per bit position

Explanation

Carry-lookahead logic derives generate and propagate terms that predict carries across groups in parallel, reducing the linear carry chain delay to roughly logarithmic depth. It does not remove carries but computes them faster at the cost of extra logic.

Question 39Digital Logic and Circuit Design

A multiplexer with 4 data inputs requires how many select lines, and what is the relationship between select lines and addressable inputs?

  1. 1 select line, since 4 inputs share a common control
  2. 3 select lines, since one is reserved for enable
  3. 4 select lines, one per data input
  4. 2 select lines, since 2^2 = 4 Correct answer.

Explanation

An N-to-1 multiplexer needs log2(N) select lines to uniquely choose among N data inputs, so four inputs require two select lines. The select code acts as a binary address for the chosen channel.

Question 40Digital Logic and Circuit Design

A static CMOS inverter drives a large capacitive load. Which design change reduces propagation delay while keeping the same logic function?

  1. Adding a series resistor between the output and the load
  2. Decreasing the transistor channel lengths and increasing device widths Correct answer.
  3. Increasing the PMOS width relative to the NMOS width
  4. Increasing the threshold voltage of both transistors

Explanation

Propagation delay scales with the load capacitance divided by the drive current. Shorter channels and wider devices raise the current available to charge and discharge the load, reducing delay.

Question 41Digital Logic and Circuit Design

What distinguishes a static RAM cell from a dynamic RAM cell at the circuit level?

  1. SRAM requires refresh cycles, while DRAM does not
  2. SRAM uses a cross-coupled latch to hold data, while DRAM uses a capacitor that must be refreshed Correct answer.
  3. SRAM uses a capacitor, while DRAM uses a cross-coupled latch
  4. SRAM is volatile, while DRAM is nonvolatile

Explanation

A six-transistor SRAM cell stores a bit in a bistable latch that holds its value as long as power is applied. A DRAM cell stores charge on a capacitor that leaks away, so periodic refresh is required.

Question 42Digital Logic and Circuit Design

A circuit must detect when a 4-bit bus equals 1011. Which combination of gates implements the equality condition most directly?

  1. A four-input XOR gate fed by the bus bits
  2. A four-input AND gate fed by the bus bits and their complements as required Correct answer.
  3. A two-input multiplexer with the bus as select lines
  4. A four-input OR gate fed by the bus bits

Explanation

Equality to a fixed pattern requires every bit to match, which is a logical AND of each bit or its complement according to the target pattern. For 1011 the AND inputs are B3, B2', B1, B0.

Question 43Digital Logic and Circuit Design

In a synchronous design, a signal generated by combinational logic must cross into a register clocked by a different, unrelated clock. What is the standard mitigation for metastability?

  1. Increase the drive strength of the sending register
  2. Route the signal through a longer combinational path
  3. Shorten the setup time of the destination register
  4. Add a multi-stage synchronizer of flip-flops clocked by the receiving clock Correct answer.

Explanation

A two- or three-stage synchronizer gives a potentially metastable signal time to resolve before it is used by downstream logic in the receiving clock domain. It reduces, but does not mathematically eliminate, the probability of failure.

Question 44Digital Logic and Circuit Design

Which device is a three-terminal, voltage-controlled switch whose channel conductivity is modulated by an insulated gate, forming the basis of most modern digital ICs?

  1. Metal-oxide-semiconductor field-effect transistor Correct answer.
  2. Junction field-effect transistor
  3. Silicon-controlled rectifier
  4. Bipolar junction transistor

Explanation

The MOSFET controls channel current through an insulated gate, drawing negligible steady gate current, which enables dense low-power CMOS logic. BJTs are current-controlled, and SCRs are latching power devices.

Question 45Operating Systems

In a preemptive priority scheduler, a low-priority task holds a mutex that a high-priority task needs. The high-priority task blocks while the low-priority task is preempted by a medium-priority task, delaying the high-priority task indefinitely. Which mechanism directly addresses this condition?

  1. Round-robin time slicing
  2. Priority inheritance Correct answer.
  3. Multilevel feedback queues
  4. Aging

Explanation

The scenario is unbounded priority inversion: a medium-priority task preempts the mutex holder and indirectly delays the high-priority waiter. Priority inheritance temporarily raises the holder's priority to that of the highest waiter so it can release the lock promptly. Aging and feedback queues address starvation of low-priority tasks, not inversion.

Question 46Operating Systems

A system uses a page table with 4 KiB pages and 32-bit virtual addresses. How many page table entries are required for a single-level page table covering the full address space?

  1. 2^12
  2. 2^32
  3. 2^44
  4. 2^20 Correct answer.

Explanation

The page offset consumes log2(4096) = 12 bits, leaving 32 - 12 = 20 bits for the virtual page number. A single-level table therefore needs 2^20 entries regardless of the physical memory size. Each entry then maps one 4 KiB page.

Question 47Operating Systems

Which structure lets a file system locate the data blocks of a very large file without storing a variable-length block list inside the inode itself?

  1. A bitmap of free blocks
  2. A multilevel index with direct, indirect, double-indirect, and triple-indirect pointers Correct answer.
  3. A journal transaction log
  4. A directory entry hash table

Explanation

Direct pointers cover small files cheaply, while single, double, and triple indirect blocks extend reach to arbitrarily large files with bounded inode size. The indirection tree grows only as the file grows. Bitmaps, directory hashes, and journals serve other purposes.

Question 48Operating Systems

A thread calls pthread_cond_wait(&cv, &m) inside a critical section. What must be true about m when the call is made, and what happens to it during the wait?

  1. m must be a recursive mutex; the call increments its recursion count.
  2. m may be in any state; the call leaves it unchanged throughout.
  3. m must be unlocked; the call locks it for the duration of the wait.
  4. m must be locked by the calling thread; the call atomically releases it and reacquires it before returning. Correct answer.

Explanation

The condition variable is designed to be used with a mutex that protects the predicate. pthread_cond_wait atomically releases the held mutex and blocks, then reacquires the mutex before returning so the predicate can be rechecked in a loop. Calling it with an unlocked mutex is undefined behavior.

Question 49Operating Systems

Under the bounded-buffer producer-consumer pattern, which pair of semaphores correctly enforces both 'do not insert into a full buffer' and 'do not remove from an empty buffer'?

  1. One mutex initialized to 1 used for both conditions
  2. empty initialized to 0 and full initialized to N
  3. A single counting semaphore initialized to N shared by both roles
  4. empty initialized to N and full initialized to 0 Correct answer.

Explanation

The empty semaphore counts free slots and starts at the buffer capacity N; the full semaphore counts filled slots and starts at 0. Producers wait on empty and post full, while consumers wait on full and post empty. This pairing blocks each side exactly when its precondition fails.

Question 50Operating Systems

A system uses 4-level page tables with 9-bit indices at each level and a 12-bit offset. What is the virtual address width?

  1. 48 bits Correct answer.
  2. 57 bits
  3. 36 bits
  4. 39 bits

Explanation

Four levels of 9-bit indices contribute 36 bits, and the 12-bit page offset adds 12 more, giving 48 bits total. This layout matches the classic 48-bit canonical address format used by common 64-bit processors. The offset is not part of the index bits.