Computer Architecture and Organization
Computer Architecture and Organization asks you to connect instruction-set design to measurable performance. Expect CPI, clock-rate, pipeline, cache, and memory-hierarchy calculations, plus qualitative trade-offs between RISC/CISC, superscalar issue, and virtual memory.
Core rules
- CPU time = instruction count × CPI × clock period. Improving one factor can hurt another.
- Pipeline speedup is limited by depth, hazards, and fill/drain; ideal speedup ≈ stages only for large workloads.
- Structural, data, and control hazards are handled by stalls, forwarding, and prediction; each adds CPI.
- Cache AMAT = hit time + miss rate × miss penalty. Split caches reduce contention but add coherence concerns.
- Amdahl’s law: speedup = 1 / ((1−f) + f/s), where f is the improved fraction.
Worked example
A program has 2.0×10^9 instructions, CPI 1.5, clock 3 GHz. CPU time = 2.0e9 × 1.5 / 3e9 = 1.0 s. If a compiler change cuts instructions by 20% but raises CPI to 1.8, new time = 1.6e9 × 1.8 / 3e9 = 0.96 s. The 4% gain shows why instruction count alone is not performance.
Cache example: hit time 1 ns, miss rate 4%, penalty 50 ns. AMAT = 1 + 0.04×50 = 3 ns. Halving miss rate to 2% gives 2 ns, a 33% latency reduction-larger than the miss-rate percentage because the base hit time remains.
Traps
- Mixing ns and cycles; convert clock rate to period first.
- Treating pipeline depth as guaranteed speedup.
- Forgetting write-back/write-through and inclusion effects when comparing caches.
- Confusing latency and throughput.