Digital Logic and Circuit Design
Digital Logic and Circuit Design tests your ability to move from Boolean specification to gate-level and sequential implementations, including timing closure.
Core rules
- Combinational logic has no state; outputs depend only on current inputs. Sequential logic stores state in latches/flip-flops.
- DeMorgan: ¬(A·B)=¬A+¬B; ¬(A+B)=¬A·¬B. Use K-maps or Quine–McCluskey to minimize SOP/POS.
- A D flip-flop samples D at the active clock edge. Setup time requires D stable before the edge; hold time requires it stable after.
- Synchronous FSMs use next-state logic, state register, and output logic; Moore outputs depend on state, Mealy on state and input.
- CMOS static power is low; dynamic power ≈ αCV²f. Glitches are combinational hazards, not fixed by adding pipeline registers alone.
Worked example
Clock period 10 ns, flip-flop clk-to-Q 1 ns, combinational delay 6 ns, setup 1.5 ns, hold 0.5 ns, clock skew 0.5 ns (capture later). Setup slack = T − t_cq − t_comb − t_setup + skew = 10 − 1 − 6 − 1.5 + 0.5 = 2 ns, so the path passes. Hold slack = t_cq + t_comb − t_hold − skew = 1 + 6 − 0.5 − 0.5 = 6 ns, also positive. If combinational delay rose to 8.5 ns, setup slack becomes −0.5 ns: the design fails until the path is pipelined or the clock is slowed.
Traps
- Sign errors in skew: launch and capture clock edges matter.
- Minimizing gate count while ignoring fan-out or wire delay.
- Confusing Mealy and Moore timing by one cycle.
- Assuming asynchronous resets are timing-exempt.