Embedded and Real-Time Systems
Embedded and Real-Time Systems tests deterministic behavior under resource constraints: interrupt handling, scheduling, timing analysis, and hardware interfacing.
Core rules
- Hard real-time misses are failures; soft real-time misses degrade quality. Correctness includes meeting deadlines, not just logical output.
- Rate-monotonic scheduling assigns higher priority to shorter periods. For n periodic tasks, utilization U=Σ(Ci/Ti); the Liu–Layland bound n(2^(1/n)−1) guarantees RM schedulability (≈69.3% for large n).
- Earliest-deadline-first is optimal for preemptive uniprocessor scheduling when U≤1, but can thrash under overload.
- Priority inversion occurs when a low-priority task holds a lock needed by a high-priority task; priority inheritance or priority ceiling protocols bound the effect.
- Interrupt latency includes hardware recognition, context save, and ISR entry. Keep ISRs short; defer work to tasks.
- Memory-mapped I/O uses volatile pointers; watchdogs recover from lockups; sleep modes trade wake latency for power.
Worked example
Tasks: T1 C=1 ms, T=4 ms; T2 C=2 ms, T=6 ms; T3 C=3 ms, T=12 ms. U=1/4+2/6+3/12=0.25+0.333+0.25=0.833. The RM bound for n=3 is 3(2^(1/3)−1)≈0.780, so the bound alone does not prove schedulability. Response-time analysis: R1=1; R2=2+ceil(6/4)×1=4≤6; R3=3+ceil(12/4)×1+ceil(12/6)×2=3+3+4=10≤12. The set is schedulable despite exceeding the sufficient bound.
Traps
- Assuming U≤1 guarantees RM schedulability.
- Ignoring blocking time from shared resources.
- Using floating-point or dynamic allocation in hard-real-time paths without WCET evidence.
- Forgetting that ISR execution consumes CPU time and can delay lower-priority work.