PRC EPLE cheat sheet

Ohm's law: V = I·R; power P = V·I = I²R = V²/R. For sinusoidal AC, RMS values are used, so average real power P = V_rms·I_rms·cos φ, where cos φ is the power factor.

Impedance: Z = R + jX. Inductive reactance X_L = 2πfL (current lags voltage by 90°); capacitive reactance X_C = 1/(2πfC) (current leads by 90°). Series resonance occurs at f₀ = 1/(2π√(LC)), where X_L = X_C and Z is purely resistive.

Quality factor Q = f₀/BW = (1/R)·√(L/C) for a series RLC circuit; bandwidth BW = f₀/Q. Higher Q means a narrower passband in filters and oscillators.

Boolean identities: De Morgan's laws (A·B)' = A' + B' and (A+B)' = A'·B'; A + A'B = A + B; A·(A+B) = A. Karnaugh maps minimize combinational logic by grouping 1s in powers of two (1, 2, 4, 8).

Semiconductor diodes: forward drop ≈ 0.7 V for silicon, ≈ 0.3 V for germanium; reverse breakdown is not normal operation except in Zener regulators, where V_Z is held constant under reverse bias.

BJT regions: cutoff (both junctions off), active (base-emitter forward, base-collector reverse; used for amplification), saturation (both forward; used as a switch). β = I_C/I_B; I_E = I_B + I_C.

MOSFET operation: enhancement-mode n-channel conducts when V_GS > V_th; in saturation I_D ≈ ½·k·(V_GS − V_th)². CMOS logic draws significant current only during switching, giving low static power.

Signal sampling: Nyquist criterion requires f_s > 2·f_max to avoid aliasing; an anti-aliasing low-pass filter precedes the ADC. ADC resolution in volts = full-scale range / 2^n for an n-bit converter.

Transmission lines: characteristic impedance Z₀ = √(L/C); a line is matched when the load equals Z₀, eliminating reflection. Reflection coefficient Γ = (Z_L − Z₀)/(Z_L + Z₀); VSWR = (1+|Γ|)/(1−|Γ|).

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