Computer Systems and Hardware
Computer Systems and Hardware covers the von Neumann model, the CPU's internal organisation, the memory hierarchy, Boolean logic and how capacity is calculated.
Core rules
- Von Neumann architecture: one memory holds both instructions and data, executed in a fetch–decode–execute cycle; the shared bus is the classic bottleneck.
- CPU: the ALU performs arithmetic and logic, the control unit sequences operations, registers (PC, IR, accumulator) hold working state, and the clock sets the pace.
- Pipelining raises throughput, not the latency of a single instruction; a branch misprediction flushes the pipeline.
- Memory hierarchy: registers → L1/L2/L3 cache → RAM → SSD/HDD. Going down, capacity and access time grow while cost per bit falls.
- RAM is volatile; ROM and flash keep data without power. Cache is managed by hardware and is not directly addressable.
- 1 KiB = 1024 B, 1 MiB = 1024 KiB. An n-bit address bus addresses 2^n cells.
- NAND is functionally complete; De Morgan: NOT(A AND B) = (NOT A) OR (NOT B).
Worked example
A system has a 12-bit address bus and a 16-bit word. Addressable cells: 2^12 = 4096. Each cell stores 16 bits = 2 bytes, so memory = 4096 × 2 B = 8192 B = 8 KiB. Reasoning: the address bus fixes how many cells exist, the data bus fixes how many bits each cell holds.
Traps
- Writing 4000 bytes because 1 KB is rounded to 1000.
- Swapping the roles of the address bus (which cell) and the data bus (how much).
- Assuming a larger cache raises clock frequency - it reduces stalls.
- Claiming RAM retains data after shutdown, or that ROM is ordinary writable memory.
- Forgetting that adding one address bit doubles the address space.