BCS Written EEE (892) cheat sheet

Ohm's law: V = IR; power P = VI = I²R = V²/R for a resistor.

Kirchhoff's current law (KCL): algebraic sum of currents at a node is zero; Kirchhoff's voltage law (KVL): algebraic sum of voltages around a closed loop is zero.

Thevenin's theorem: any linear two-terminal network can be replaced by an equivalent voltage source V_th in series with R_th, where V_th is the open-circuit voltage and R_th is the resistance seen with independent sources deactivated.

Norton's theorem: equivalent current source I_N in parallel with R_N; I_N is the short-circuit current and R_N = R_th.

Superposition applies only to linear circuits: response = sum of responses to each independent source acting alone with others deactivated (voltage sources shorted, current sources opened).

Maximum power transfer to a load occurs when R_L = R_th (DC) or Z_L = Z_th* (AC); efficiency at maximum power transfer is 50% for a resistive DC source.

First-order RC circuit: time constant τ = RC; capacitor voltage v_C(t) = V_∞ + (V_0 − V_∞)e^(−t/τ). RL circuit: τ = L/R; inductor current i_L(t) = I_∞ + (I_0 − I_∞)e^(−t/τ).

RLC series resonance: f_0 = 1/(2π√(LC)); quality factor Q = (1/R)√(L/C) = f_0/BW; bandwidth BW = f_0/Q.

Two-port network parameters: z-parameters V1 = z11 I1 + z12 I2, V2 = z21 I1 + z22 I2; for a reciprocal network z12 = z21.

DC machine EMF: E = (PΦNZ)/(60A), where P = poles, Φ = flux per pole, N = speed in rpm, Z = total armature conductors, A = number of parallel paths (A = P for lap, A = 2 for wave).

DC motor torque: T = (PΦI_a Z)/(2πA) = 9.55 × P_out/N (N·m); back EMF E_b = V − I_a R_a.

Transformer EMF equation: E = 4.44 f N Φ_m; turns ratio a = N1/N2 = V1/V2 ≈ I2/I1.

Transformer equivalent circuit: referred secondary impedance to primary is multiplied by a²; core-loss resistance R_c represents hysteresis and eddy-current losses; magnetizing reactance X_m represents magnetizing current.

Induction motor synchronous speed: N_s = 120f/P; slip s = (N_s − N_r)/N_s; rotor frequency f_r = s f.

Three-phase induction motor torque: T = (3/ω_s) × [s E_2² R_2 / (R_2² + (s X_2)²)] referred to stator; maximum torque occurs at s = R_2/X_2.

Synchronous machine: E_f = V_t + j I_a X_s (cylindrical rotor, per phase, neglecting R_a); power P = (3 V_t E_f / X_s) sin δ.

Transformer losses: copper loss = I²R (varies with load squared); core loss is approximately constant at rated voltage and frequency; efficiency is maximum when copper loss equals core loss.

Per-unit system: Z_pu = Z_actual / Z_base; Z_base = V_base² / S_base (three-phase); change of base: Z_pu,new = Z_pu,old × (S_new/S_old) × (V_old/V_new)².

Short transmission line (length < 80 km): ABCD parameters A = D = 1, B = Z, C = 0; medium line (80–250 km) uses nominal-π or nominal-T model.

Surge impedance of a lossless line: Z_c = √(L/C); surge impedance loading SIL = V_L² / Z_c.

Power flow on a short line: P = (V_s V_r / X) sin δ; Q = (V_s V_r / X) cos δ − V_r²/X; maximum power at δ = 90°.

Symmetrical components: positive, negative, and zero sequence; a = 1∠120°; I_a0 = (I_a + I_b + I_c)/3; zero-sequence currents require a neutral return path.

Protection: overcurrent relay coordination uses time-multiplier settings; distance relay zones: Zone 1 ≈ 80% of line, Zone 2 ≈ 120–150%, Zone 3 covers remote backup.

Circuit breaker rating: symmetrical interrupting current plus DC component; making current peak = 2.55 × symmetrical rms for a fully offset wave.

Transmission line voltage regulation = (|V_r,noload| − |V_r,fullload|)/|V_r,fullload| × 100%; Ferranti effect raises receiving-end voltage on lightly loaded long lines.

Thyristor conduction: triggered by gate current when forward-biased; turns off when anode current falls below holding current; latching current is the current needed to keep it on immediately after turn-on.

Single-phase fully controlled bridge with resistive load: V_dc = (2V_m/π) cos α; with highly inductive load and freewheeling diode, V_dc = (2V_m/π) cos α for 0 ≤ α ≤ 90°.

Three-phase fully controlled bridge: V_dc = (3√3 V_m/π) cos α = 1.35 V_LL cos α (where V_LL is line-to-line rms).

Buck converter (continuous conduction): V_o = D V_s; boost converter: V_o = V_s/(1 − D); buck-boost: V_o = −V_s D/(1 − D).

DC motor speed control: N ∝ (V_a − I_a R_a)/Φ; armature voltage control gives constant-torque operation below base speed; field weakening gives constant-power operation above base speed.

Induction motor variable-frequency drive: V/f control maintains constant flux below base speed; above base speed, voltage is held constant and flux weakens.

PWM inverter: modulation index m = V_control/V_triangle; fundamental output voltage (linear region, m ≤ 1) V_1 = m V_dc/2 for a half-bridge; for a full bridge V_1 = m V_dc.

Snubber circuits protect switching devices: RC snubber across a thyristor limits dv/dt; a series inductor limits di/dt.

Transfer function G(s) = Y(s)/U(s) for zero initial conditions; closed-loop transfer function with unity feedback is G/(1 + G).

Second-order system: ω_n = natural frequency, ζ = damping ratio; characteristic equation s² + 2ζω_n s + ω_n² = 0; percent overshoot = 100 e^(−ζπ/√(1−ζ²)); settling time (2%) ≈ 4/(ζω_n).

Routh–Hurwitz criterion: number of sign changes in the first column of the Routh array equals the number of right-half-plane poles.

Steady-state error: for a step input, e_ss = 1/(1 + K_p); ramp input, e_ss = 1/K_v; parabolic input, e_ss = 1/K_a, where K_p = lim_{s→0} G(s), K_v = lim_{s→0} sG(s), K_a = lim_{s→0} s²G(s).

Bode plot: gain margin = negative of the gain (dB) at the phase crossover frequency (phase = −180°); phase margin = 180° + phase at the gain crossover frequency (gain = 0 dB).

PID controller: u(t) = K_p e(t) + K_i ∫e dt + K_d de/dt; integral action eliminates steady-state error; derivative action increases damping and reduces overshoot.

Strain gauge: gauge factor GF = (ΔR/R)/(ΔL/L); Wheatstone bridge converts resistance change to voltage; quarter-bridge output V_o ≈ (V_ex/4) × GF × ε.

Instrumentation: accuracy = closeness to true value; precision = repeatability; resolution = smallest detectable change; a 3½-digit DMM has 1999 counts.

PN-junction diode: Shockley equation I_D = I_s(e^(V_D/(nV_T)) − 1); thermal voltage V_T ≈ 26 mV at 300 K; forward drop ≈ 0.7 V for silicon, 0.3 V for germanium.

BJT regions: cutoff (V_BE < 0.7 V), active (V_BE ≈ 0.7 V, V_CE > 0.2 V), saturation (V_CE ≈ 0.2 V); β = I_C/I_B; α = β/(1 + β).

MOSFET: in saturation, I_D = ½ k_n (V_GS − V_th)² (with channel-length modulation neglected); in triode, I_D = k_n[(V_GS − V_th)V_DS − V_DS²/2].

Op-amp ideal assumptions: infinite open-loop gain, infinite input impedance, zero output impedance; virtual short (V+ = V−) applies with negative feedback.

Inverting amplifier gain = −R_f/R_in; non-inverting gain = 1 + R_f/R_in; integrator: V_o = −(1/RC)∫V_i dt; differentiator: V_o = −RC dV_i/dt.

Common-emitter amplifier: voltage gain ≈ −g_m R_C (or −R_C/r_e); input resistance ≈ β r_e; output resistance ≈ R_C.

Rectifiers: half-wave V_dc = V_m/π; full-wave V_dc = 2V_m/π; ripple factor for capacitor-filtered full-wave rectifier ≈ 1/(4√3 f C R_L).

Zener regulator: series resistor R_s = (V_in − V_Z)/(I_Z + I_L); Zener must remain reverse-biased above V_Z.

Boolean identities: A + A'B = A + B; A + AB = A; De Morgan: (A + B)' = A'B', (AB)' = A' + B'.

Karnaugh map grouping: groups must contain 1, 2, 4, 8, … adjacent cells; larger groups yield simpler terms; don't-cares may be included to enlarge groups.

Combinational building blocks: 2-to-1 multiplexer F = S' I_0 + S I_1; 1-bit full adder S = A ⊕ B ⊕ C_in, C_out = AB + AC_in + BC_in.

Flip-flops: D flip-flop Q(next) = D; JK flip-flop Q(next) = JQ' + K'Q; T flip-flop toggles when T = 1.

Number systems: binary-to-decimal by positional weights; hexadecimal digit = 4 bits; BCD uses 4 bits per decimal digit; Gray code changes one bit between adjacent codes.

Signed number representations: two's complement range for n bits is −2^(n−1) to 2^(n−1) − 1; negation is bitwise complement plus 1.

Sequential circuit design: state diagram → state table → state assignment → excitation table → K-map simplification → flip-flop inputs.

Memory: ROM is nonvolatile; RAM is volatile; address lines m give 2^m locations; data lines n give word width n bits.

8085 microprocessor: 8-bit data bus, 16-bit address bus, 64 KB address space; clock 3 MHz; registers A, B, C, D, E, H, L; flags S, Z, AC, P, CY.

8086 microprocessor: 16-bit data bus, 20-bit address bus, 1 MB address space; memory segmented into 64 KB segments; physical address = segment × 16 + offset.

Instruction cycle phases: fetch, decode, execute; machine cycle consists of T-states; 8085 instruction timing given in T-states (e.g., MOV r, r = 4 T-states).

Interrupts: 8085 has TRAP (highest priority), RST 7.5, 6.5, 5.5, INTR (lowest); vectored interrupts have fixed addresses.

Memory-mapped I/O uses the same address space as memory; port-mapped I/O uses separate IN/OUT instructions and port addresses.

Embedded system characteristics: dedicated function, real-time constraints, limited memory and power; common architectures include ARM Cortex-M and AVR.

Serial protocols: UART asynchronous with start/stop bits; SPI synchronous full-duplex with master/slave and chip select; I²C two-wire (SDA, SCL) with addressing.

Watchdog timer resets the processor if firmware fails to clear it within a set interval, preventing lock-up in embedded systems.

AM: modulation index μ = A_m/A_c; total power P_t = P_c(1 + μ²/2); bandwidth = 2 f_m; DSB-SC and SSB bandwidths are 2 f_m and f_m respectively.

FM: modulation index β = Δf/f_m; Carson's rule bandwidth ≈ 2(Δf + f_m); FM improves noise immunity at the cost of bandwidth.

Shannon–Hartley capacity: C = B log₂(1 + S/N) bits/s; Nyquist sampling rate f_s ≥ 2 f_max to avoid aliasing.

PCM: quantization noise power = Δ²/12; signal-to-quantization-noise ratio (SQNR) ≈ 6.02 n + 1.76 dB for a full-scale sinusoid with n bits.

Digital modulation: BPSK and QPSK have the same bit-error-rate performance in AWGN (QPSK carries two bits per symbol); 16-QAM requires higher SNR for the same BER.

DFT: X[k] = Σ_{n=0}^{N−1} x[n] e^(−j2πkn/N); FFT reduces computation from O(N²) to O(N log₂ N).

LTI systems: convolution in time equals multiplication in frequency; a system is stable if its impulse response is absolutely summable (BIBO stability).

Antenna: half-wave dipole length ≈ 0.5λ; free-space wavelength λ = c/f; Friis transmission equation P_r = P_t G_t G_r (λ/(4πd))².

OSI seven layers (bottom up): Physical, Data Link, Network, Transport, Session, Presentation, Application; TCP/IP model merges Session, Presentation, and Application into Application.

IPv4 address: 32 bits, dotted decimal; private ranges 10.0.0.0/8, 172.16.0.0/12, 192.168.0.0/16; subnet mask /24 gives 254 usable hosts.

TCP is connection-oriented and reliable with three-way handshake (SYN, SYN-ACK, ACK); UDP is connectionless and unreliable with lower overhead.

Ethernet CSMA/CD: minimum frame size 64 bytes; maximum 1518 bytes with VLAN tag; MAC address is 48 bits.

Routing: distance-vector protocols (RIP) use hop count; link-state protocols (OSPF) use Dijkstra's algorithm; BGP is the inter-domain routing protocol.

Software engineering: waterfall is sequential; agile uses iterative sprints; version control (Git) tracks changes with commits, branches, and merges.

ICT applications: databases use SQL for relational queries; cloud service models are IaaS, PaaS, SaaS; virtualization abstracts hardware resources.

Network security: symmetric encryption (AES) uses one shared key; asymmetric encryption (RSA) uses public/private key pairs; hashing (SHA-256) provides integrity.

Laplace transforms: L{1} = 1/s, L{e^(−at)} = 1/(s+a), L{sin ωt} = ω/(s²+ω²), L{cos ωt} = s/(s²+ω²); derivative L{f'(t)} = sF(s) − f(0).

Fourier series for period 2π: f(x) = a₀/2 + Σ(a_n cos nx + b_n sin nx); coefficients a_n = (1/π)∫f(x)cos nx dx, b_n = (1/π)∫f(x)sin nx dx over one period.

Matrix: determinant of 2×2 [[a,b],[c,d]] is ad − bc; inverse exists if determinant ≠ 0; eigenvalues solve det(A − λI) = 0.

Probability: P(A∪B) = P(A) + P(B) − P(A∩B); Bayes' theorem P(A|B) = P(B|A)P(A)/P(B).

Calculus: d/dx(x^n) = n x^(n−1); ∫x^n dx = x^(n+1)/(n+1) + C (n ≠ −1); product rule (uv)' = u'v + uv'.

Numerical methods: Newton–Raphson iteration x_{n+1} = x_n − f(x_n)/f'(x_n); trapezoidal rule ∫_a^b f(x)dx ≈ (h/2)[f(a) + 2Σf(x_i) + f(b)].

Complex numbers: Euler's formula e^(jθ) = cos θ + j sin θ; magnitude of a + jb is √(a² + b²); argument is tan⁻¹(b/a).

Differential equations: first-order linear dy/dx + P(x)y = Q(x) has integrating factor e^(∫P dx).

Project management: critical path is the longest duration path through the network; total float = LS − ES = LF − EF; critical activities have zero float.

CPM/PERT: PERT uses three time estimates (optimistic, most likely, pessimistic); expected time t_e = (a + 4m + b)/6; variance = ((b − a)/6)².

Break-even analysis: break-even quantity Q = F/(P − V), where F = fixed cost, P = unit price, V = variable cost per unit.

Depreciation: straight-line D = (C − S)/n; declining balance uses a fixed percentage of book value each year.

Engineering ethics: paramount obligation is public safety, health, and welfare; engineers must disclose conflicts of interest and avoid deceptive practices.

Professional codes (e.g., IEEE, ASCE) require competence only in one's field, confidentiality of proprietary information, and giving credit for others' work.

Contract types: lump-sum (fixed price) shifts cost risk to contractor; cost-plus shifts risk to owner; unit-price is used for uncertain quantities.

Quality management: PDCA cycle (Plan–Do–Check–Act); ISO 9001 specifies quality management system requirements.