ENADE Engenharia Elétrica common mistakes
ENADE Engenharia Elétrica · Understand the traps and how to avoid them.
On ethics and citizenship items, the candidate picks the alternative that sounds most morally elevated or most legally severe, instead of the one that matches the constitutional or statutory principle actually described in the stem.
General-formation ethics items are often built around a tension (individual right vs. collective interest, public transparency vs. privacy). Candidates answer from personal opinion or from a vague sense of 'the correct civic attitude' rather than from the normative framework (CF/1988 principles, public-administration legality/impersonality/morality/publicity/efficiency, consumer or environmental law duties).
What to do instead
Before choosing, identify in the stem which normative source is being invoked and which value is in conflict. Rehearse the core principles explicitly: legality, impersonality, morality, publicity and efficiency in public administration; dignity of the human person and solidarity in the constitutional order; the polluter-pays and prevention principles in environmental law. Eliminate options that resolve the conflict by absolutizing one side or that describe a personal moral judgment rather than a legal duty.
On globalization, public policy and sustainable-development items, the candidate treats 'sustainable' as a synonym for 'environmental only' and discards options that combine economic, social and environmental dimensions, or accepts options that promise zero-cost, zero-conflict solutions.
The sustainability concept is frequently reduced to its ecological pillar in everyday discourse, while the exam works with the triple bottom line and with the idea of meeting present needs without compromising future generations. Candidates also gravitate to options with absolute language ('eliminates', 'guarantees for all', 'immediately') because they sound decisive.
What to do instead
Anchor every answer on the three pillars (economic viability, social equity, environmental protection) plus the institutional dimension where relevant. Treat absolute or cost-free promises as red flags. Practice classifying real Brazilian policy cases (sanitation framework, solid-waste policy, renewable-auction incentives) by which pillar each measure primarily addresses and which trade-offs it creates.
On reading and interpretation items, the candidate answers from prior knowledge of the topic or from the general theme of the text rather than from what the text actually asserts, and misreads the command verb (infer vs. conclude vs. identify the author's thesis).
Under time pressure, candidates skim the stem and the first lines of the text, recognize a familiar subject, and select the option that is true in the world but not supported by the passage. Modality markers ('pode', 'deve', 'sempre', 'em geral') and concessive constructions are also routinely overlooked, inverting the author's position.
What to do instead
Read the command verb first, then locate the exact sentence in the text that supports each candidate option, marking it as supported, contradicted or absent. Reject any option whose content is true but not derivable from the passage. Train on modality: underline every 'sempre', 'nunca', 'apenas', 'pode' in options, because these are the words that make an otherwise plausible option wrong.
In circuit problems, the candidate writes mesh or nodal equations directly from the schematic without first fixing reference directions, then reports a negative or algebraically inconsistent result and 'corrects' the sign by hand to match the expected answer.
Passive-sign convention is applied inconsistently: current arrows and voltage polarities are assigned ad hoc per element, dependent sources are treated as independent during equation assembly, and the candidate lacks a routine consistency check (power balance, KCL at a node, superposition cross-check). Sign errors are then rationalized rather than diagnosed.
What to do instead
Adopt a fixed procedure: label all node voltages relative to one declared reference, assign branch currents in the passive convention, then write equations mechanically. For dependent sources, keep the controlling variable as an unknown and add its defining equation. Close every problem with a power-balance check (sum of absorbed power equals sum of delivered power) or a KCL verification at one node; if it fails, the error is algebraic, not conceptual.
In transient and AC steady-state analysis, the candidate applies DC intuition to reactive circuits, treating the capacitor as an open circuit or the inductor as a short at the wrong time, or equating the time constant with the settling time without converting.
The three regimes (initial state at t = 0+, steady state at t → ∞, and the transient in between) are conflated. Candidates memorize 'capacitor open, inductor short' without conditioning it on DC steady state, and they confuse τ with the 5τ settling convention or with the half-power bandwidth relation.
What to do instead
For every transient problem, explicitly tabulate vC(0+), iL(0+), vC(∞), iL(∞) and τ before writing the exponential. Memorize that the response reaches about 63% of the final change in one τ and is conventionally settled at 5τ. For AC, convert to phasors, compute the complex impedance of each reactive element at the given frequency, and verify that the result reduces to the DC limit as ω → 0.
In analog electronics, the candidate assumes the operational amplifier is ideal and in linear negative feedback in every configuration, applying the virtual-short rule even to comparator, Schmitt-trigger, integrator-with-saturation or positive-feedback circuits.
The virtual-short rule is over-learned as a universal law rather than as a consequence of infinite gain plus negative feedback. Candidates also ignore output voltage rails and slew-rate limits, so they accept results that exceed the supply or that require an impossible output swing.
What to do instead
Before applying virtual short, verify two conditions explicitly: negative feedback is present and the required output lies within the supply rails. If either fails, analyze the circuit as a comparator with saturated output. Always compare the computed output against the rails as a final sanity check, and treat rail-limited results as a signal that the operating mode assumption was wrong.
In digital electronics, the candidate designs combinational logic without a complete truth table or Karnaugh map and delivers a circuit that is functionally correct for the listed input combinations but fails on don't-care or unused states, or ignores fan-out, propagation delay and setup/hold constraints.
The candidate jumps from the verbal specification to a gate diagram, skipping the canonical minimization step, and treats timing as a secondary concern. Static hazards and asynchronous input problems are invisible in a purely functional mental model.
What to do instead
Always derive the truth table first, fill don't-cares deliberately (and state the choice), minimize with a Karnaugh map or Boolean algebra, then implement. For sequential or mixed designs, check setup and hold against the stated clock period and propagation delays, and check the unused-state behavior of any state machine. Verify the final circuit against the truth table row by row.
In electric machinery and drives, the candidate computes slip, torque or efficiency using rated values as if they held at every operating point, ignoring that flux, saturation and rotor resistance change with load and temperature, and mixes per-phase and three-phase quantities.
The equivalent circuit is memorized as a fixed set of numbers rather than as a model whose parameters depend on operating condition. Candidates also lose track of whether a power quantity is per phase or total, and whether a voltage is line-to-line or phase, especially in delta and wye conversions.
What to do instead
State at the top of each solution whether quantities are per phase or three phase and whether voltages are line or phase, then convert once, explicitly. Use the equivalent circuit with slip as the independent variable and derive torque from the air-gap power, not from nameplate ratios. Sanity-check efficiency against the loss breakdown (copper, core, mechanical) and confirm that the result lies in a physically plausible range.
In power systems and protection, the candidate performs per-unit or load-flow calculations without declaring base power and base voltage consistently, and sets protective relay pickup or time-dial values from the load current rather than from fault current coordination.
Per-unit conversion is treated as an arithmetic formality, so bases are changed midway or mixed between zones separated by transformers. In protection, the candidate reasons from normal operating current, which yields settings that are either blind to faults or that trip on legitimate overloads, and neglects CT ratio and coordination margins.
What to do instead
Write the base power and base voltage for every zone before any calculation, convert all impedances to the chosen base in one pass, and verify that the per-unit fault current times base current matches the physical expectation. For protection, start from the fault-current study, apply the CT ratio explicitly, then check sensitivity (pickup below minimum fault current) and selectivity (time grading against the downstream device) as two separate tests.
In control and instrumentation items, the candidate evaluates a control loop by steady-state gain alone, ignoring stability margins, sensor dynamics and noise, and in signal-processing items applies the sampling theorem as a formality without checking for aliasing or spectral leakage in the stated measurement setup.
Block-diagram algebra is performed correctly while the physical meaning of the loop is lost: phase margin, sensor bandwidth and transducer noise are not connected to the block diagram. Similarly, the Nyquist criterion is recited but not applied to the actual sampling rate and signal content given in the stem.
What to do instead
For every control problem, compute the open-loop frequency response and report gain margin and phase margin alongside the steady-state error; check that sensor bandwidth exceeds the loop crossover frequency. For sampling problems, compute the Nyquist frequency explicitly, list every frequency component present in the signal, and flag any component above it as an alias before choosing an option.