48 V PoE Buck Converter Overheats and Fails EMC
A 48 V Power-over-Ethernet input, 5 V/3 A output buck converter is built on a 100 mm × 80 mm four-layer PCB inside a sealed IP54 enclosure. The converter switches at 400 kHz, uses a 10 µH shielded inductor and a 25 mΩ MOSFET. The hot loop between input capacitors and switch node is about 12 mm long; the MOSFET thermal pad connects to the inner ground plane through four 0.3 mm vias. At 25 °C room ambient, the MOSFET case reaches 118 °C after 20 minutes at full load; the calculated junction temperature is about 150 °C. Output ripple is 220 mV peak-to-peak, and radiated emissions exceed EN 55032 Class B limits by 6 dB at 48 MHz and 96 MHz. When a 30 m Ethernet cable is connected, the board resets intermittently. There is no common-mode choke, and the shield of the RJ45 is tied directly to digital ground. The enclosure cannot be enlarged and forced air cooling is not permitted. The board must pass Class B and operate at 50 °C ambient.
1. Assess whether the measured thermal performance is credible and establish the loss and thermal budget needed for 50 °C operation.
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At 15 W output, 90% efficiency gives about 1.7 W loss. With a small board and only four thermal vias, a junction-to-ambient resistance of 50–60 K/W is plausible, so a 118 °C case at 25 °C ambient is credible. But 150 °C junction leaves no margin at 50 °C ambient: to keep junction below 125 °C, the allowable rise is only about 75 K. If RθJA is 55 K/W, loss must be below about 1.35 W; for a 15 K margin, below 1.1 W. The 12 mm hot loop and single via per ground pad increase switching loss and EMI. The 220 mV ripple suggests insufficient output capacitance or excessive ESR/ESL. The 48 and 96 MHz peaks are consistent with 400 kHz harmonics and cable common-mode resonance. The reset with the Ethernet cable indicates common-mode noise injecting into digital ground through the RJ45 shield.
2. Prioritise layout and EMI fixes that do not increase board area. Explain why each fix comes in that order.
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First improve the thermal path: replace the four 0.3 mm vias with a 3 × 3 or 4 × 4 array of 0.3 mm vias under the pad, add copper pour on the bottom and both inner layers, and keep thermal relief only where manufacturability requires it. This is cheap and does not increase area. Second shrink the hot loop: move input capacitors within 3 mm of the switch, tighten the return path, and measure before adding a snubber. Third address common-mode EMI: add a common-mode choke or ferrite bead on the Ethernet pair, connect the RJ45 shield to chassis through a 1 nF/1 MΩ network, and keep digital ground separate from chassis. Fourth reduce output ripple with additional 22 µF ceramic capacitance or a small LC filter. Thermal vias and hot-loop layout come first because they address overheating and EMI together; component additions are last because they add cost and can create new resonances.
3. Define the verification plan and acceptance criteria.
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Verify at 50 °C chamber temperature, full load, at 48 V and 36 V input, with a 30 m Ethernet cable. Measure MOSFET case and inductor temperature until stable, output ripple with 20 MHz bandwidth, and radiated emissions from 30 MHz to 1 GHz in a pre-compliance scan. Run a four-hour thermal soak and 1,000 load transients. Check reset immunity by injecting common-mode noise on the Ethernet cable and by ESD and surge on the RJ45. Acceptance: junction below 110 °C at 50 °C ambient with at least 15 K margin, ripple below 50 mV, Class B margin of at least 6 dB, and no reset. If thermal vias alone do not achieve this, reduce switching frequency or use a lower-Rds(on) device. Do not rely on the enclosure as a heat sink, because the IP54 seal limits convection.