Electronic Circuit and System Design
Electronic Circuit and System Design tests whether you can produce a circuit that works across tolerance, temperature, supply and load variation, and still meets safety and EMC limits. The exam favours worst-case reasoning over nominal simulation.
Analog and mixed-signal design
Treat op-amp circuits with input offset voltage, bias current, gain-bandwidth product, slew rate, noise and stability. Check phase margin with the actual load capacitance; a unity-gain buffer driving a capacitive load may need isolation. Use metal-film or thin-film resistors where drift matters, and account for capacitor derating (X7R loses capacitance under DC bias and temperature). Separate analog and digital return currents and define a star or plane strategy deliberately.
Digital, power and signal integrity
Check setup/hold timing at all corners, clock domain crossings and metastability. Level translators are needed when a 3.3 V LVCMOS output drives a 5 V CMOS input whose VIH is 3.5 V; a direct connection is not guaranteed. Provide decoupling with low-inductance return paths, and check the power distribution network impedance over frequency, not just the capacitor count. Use series termination or controlled-impedance traces when the rise time is short relative to the trace delay; keep return current paths continuous.
Safety and manufacturability
For mains-facing circuits, apply IEC 62368-1 isolation requirements: creepage, clearance, solid insulation, Y-capacitor rating and hi-pot test. Pollution degree and material group change the required dimensions. Design for manufacture and test: test points, bed-of-nails access, panelisation, component availability and derating.
Worked example
A 3.3 V driver feeds a 5 V CMOS gate with VIH = 3.5 V over a 20 cm ribbon at 10 MHz. The DC calculation shows the driver's VOH may be only 3.0 V under load, below 3.5 V, so the link is invalid. A level shifter is required. The 20 cm ribbon also has significant inductance; add a series resistor at the source and a local return path. Do not fix only the DC level and ignore the transient ringing.
Traps
Using absolute maximum ratings as design targets; assuming nominal 3.3 V or 5 V rails; ignoring capacitor DC bias; forgetting the return path; specifying a safety clearance without checking pollution degree; and validating only at room temperature.