Bias-Point Drift in a Common-Source NMOS Stage
A discrete common-source NMOS stage is biased with VDD = 5 V, RD = 10 kΩ, RS = 1 kΩ, and a gate bias of VG = 1.50 V. The design assumes Vt = 0.70 V, kn′ = 200 µA/V², W/L = 10, and λ = 0.02 V⁻¹. The intended quiescent output is near 2.2 V. On a batch of parts, the measured output sits at 4.10 V, the source voltage at 0.09 V, and small-signal gain falls from the simulated 8 V/V to about 2 V/V. The gate bias is verified at 1.50 V and RD/RS are within 1%. The supply is clean. The lab asks whether the parts are counterfeit, whether the stage has entered triode, and what can be trimmed at test to recover headroom and gain.
1. Calculate the intended quiescent current and verify whether the original design was in saturation.
Read the worked answer
Use the saturation square law with kn = kn′(W/L) = 200 µA/V² × 10 = 2 mA/V². Let ID be in mA. Then VGS = 1.50 − ID(1 kΩ) and
ID = (kn/2)(VGS − Vt)² = 1(0.80 − ID)².
This gives ID² − 2.60ID + 0.64 = 0. The physically valid root is ID ≈ 0.276 mA. Hence VS = 0.276 V, VD = 5 − 0.276 × 10 = 2.24 V, and VDS = 1.96 V. The overdrive is Vov = VGS − Vt = (1.50 − 0.276) − 0.70 = 0.524 V. Since VDS = 1.96 V > Vov = 0.524 V, the original design is comfortably in saturation. The expected output is therefore about 2.24 V, not 4.10 V.
2. Using the measured voltages, diagnose whether the batch is in triode or has a shifted threshold. Support the conclusion numerically.
Read the worked answer
Measured drain current is ID = (5 − 4.10)/10 kΩ = 90 µA, and VS = 0.09 V, consistent with the 1 kΩ source resistor. If the device were in saturation, then
90 µA = (2 mA/V²)/2 × (1.50 − 0.09 − Vt)²,
so (1.41 − Vt)² = 0.09 and Vt ≈ 1.11 V. Check saturation: VDS = 4.10 − 0.09 = 4.01 V, while Vov = 1.41 − 1.11 = 0.30 V. Since VDS > Vov, the device is still in saturation, not triode. The observed behaviour is therefore consistent with a threshold shift of about +0.4 V, not automatically with counterfeit parts. The lower current reduces gm and hence gain; the measured 2 V/V also suggests extra loading or that the square-law model is optimistic.
3. Recommend a test-time trim to restore the intended bias, and state the trade-off.
Read the worked answer
To restore ID ≈ 0.276 mA with Vt ≈ 1.11 V, the required overdrive is Vov = sqrt(2ID/kn) = sqrt(0.276/1) ≈ 0.525 V. Then VGS = Vt + Vov ≈ 1.635 V. Since VS = ID × 1 kΩ ≈ 0.276 V, the gate must be raised to VG ≈ 1.91 V, about 0.40 V above the present 1.50 V. Alternatively, reduce RS or increase W/L, but increasing W/L also raises capacitance and may reduce bandwidth. Raising VG is the cleanest trim if the bias network allows it. Recheck saturation after the trim: VDS ≈ 5 − 0.276 × 11 ≈ 1.96 V, safely above Vov. The trade-off is reduced output headroom and increased drain current, so verify power and the downstream load.