GATE EC study plan

GATE EC · Give each week a clear focus.

8 weeks · About 6 hours per week

Week 1

Electronics and Communication Engineering (GATE paper)

Derive and memorize the small-signal models for BJT and MOSFET, including hybrid-pi parameters and transconductance relationships.
Solve 15 single-stage amplifier problems covering CE, CB, CC, CS, CG, and CD configurations, computing gain, input resistance, and output resistance.
Set up a formula sheet for transistor biasing that distinguishes cutoff, active, and saturation regions for both device types.
Establish a timed problem-solving log that records error type (sign, algebra, concept) for every wrong answer.

A one-page hand-written transistor cheat sheet plus a 15-problem error log with each mistake classified.

Week 2

Analyze op-amp circuits including inverting, non-inverting, integrator, differentiator, and instrumentation configurations using ideal and finite-gain models.
Compute slew-rate, gain-bandwidth, and offset limitations for at least 8 op-amp problems.
Design and verify active filter topologies (first-order low-pass, high-pass, and band-pass) symbolically.
Practice 10 numerical problems on feedback topologies and identify the feedback type in each.

A timed 90-minute mock set of 20 analog problems scored and reviewed, with all skipped items reworked.

Week 3

Analyze diode circuits including clippers, clampers, rectifiers, and zener regulators with numerical ripple and efficiency calculations.
Solve 12 problems on small-signal diode resistance and load-line analysis.
Review oscillators and multivibrators, deriving the Barkhausen condition and frequency of RC phase-shift and Wien-bridge oscillators.
Consolidate a second cheat sheet covering diodes, oscillators, and feedback.

A 20-question self-made quiz on diodes and oscillators with a written solution key.

Week 4

Complete a full-length timed analog section mock under exam conditions (90 minutes, no notes).
Classify all errors by subtopic and rank the three weakest subtopics.
Rework every missed problem to a clean solution without referring to the answer key.
Update the cheat sheet with any missing formulas discovered during the mock.

Mock score report with an error taxonomy and a ranked list of the three weakest analog subtopics.

Week 5

Master combinational logic design: K-map minimization, multiplexer and decoder implementation, and static hazard identification.
Design and analyze sequential circuits including flip-flops, counters, and shift registers, and derive state diagrams.
Solve 10 problems on setup and hold time, clock skew, and maximum operating frequency.
Convert between number systems and perform fixed-point and floating-point arithmetic in 8 problems.

A complete set of state diagrams and timing analyses for 6 sequential circuits, each verified against a truth-table check.

Week 6

Analyze continuous-time and discrete-time LTI systems using convolution, impulse response, and transfer functions.
Compute Fourier series, Fourier transform, Laplace transform, and z-transform for standard signals and use them to solve 15 problems.
Determine stability and causality of systems from pole-zero locations, including ROC analysis.
Solve 8 problems on sampling, aliasing, and the Nyquist criterion.

A transform-pair reference sheet plus 15 fully worked transform problems with ROC noted for each.

Week 7

Review communication systems fundamentals: AM and FM modulation, bandwidth, and demodulation, solving 10 numerical problems.
Compute Shannon capacity, quantization noise, and PCM bit rates in 8 problems.
Review random variables and noise analysis, including Gaussian noise and SNR calculations.
Review control systems basics: transfer functions, Routh-Hurwitz stability, and Bode plot interpretation.

A timed 45-minute quiz on communications and control fundamentals with a written correction log.

Week 8

Take two full-length timed GATE-style mocks covering the full syllabus and record section-wise scores.
Rework every incorrect or guessed item from both mocks until each can be solved unaided.
Revise all cheat sheets and formula references in a single consolidated pass.
Simulate exam-day pacing by allocating time per section and practicing the skip-and-return strategy.

Final consolidated formula booklet plus a mock score comparison showing improvement from week 4 to week 8.

Week 2: Score at least 60% on the timed 20-problem analog mock and be able to derive small-signal models from memory without notes.

Week 4: Complete the full analog mock within 90 minutes with at least 65% accuracy, and have reworked all missed problems to clean solutions.

Week 6: Solve 12 of 15 transform problems correctly and correctly identify ROC and stability for every pole-zero case attempted.

Week 8: Achieve at least 70% on the final full-length mock with no section below 50%, and finish the consolidated formula booklet.