GATE EC case studies
GATE EC · Put your knowledge to work in context.
GATE Electronics and Communication Engineering (GATE EC) is the discipline-specific paper of the Graduate Aptitude Test in Engineering, a national postgraduate engineering entrance examination in India. The official source available for this page, the IIT Guwahati website, lists GATE/JAM among the pages it offers to prospective students, confirming that GATE is administered within the IIT system; it does not publish GATE EC question counts, duration, fees, or qualifying marks, so those details must be confirmed on the official GATE portal for your year. The GATE EC case studies are 5 cases and about 2,496 words.
1Bias-Point Drift in a Common-Source NMOS Stage
A discrete common-source NMOS stage is biased with VDD = 5 V, RD = 10 kΩ, RS = 1 kΩ, and a gate bias of VG = 1.50 V. The design assumes Vt = 0.70 V, kn′ = 200 µA/V², W/L = 10, and λ = 0.02 V⁻¹.
547 words, about 3 min2Setup and Hold Judgement on a 200 MHz Synchronous Path
A 200 MHz synchronous block (T = 5.00 ns) contains a launch flop and a capture flop on the same clock, but the capture clock arrives 0.30 ns later than the launch clock. For the suspect path, the flop clk-to-Q delay is 0.40 ns maximum and 0.15 ns minimum, the combinational network is 4.80 ns maximum and 0.35 ns minimum, setup time is 0.20 ns, and hold time is 0.10 ns.
522 words, about 3 min3Aliasing and Anti-Alias Filter Adequacy at 8 kHz Sampling
An 8.00 kHz sampler feeds a 12-bit ADC. The wanted channel is at 1.20 kHz.
473 words, about 2 min4QPSK Constellation Distortion: IQ Imbalance Versus Phase Noise
A QPSK link runs at Rs = 20 Msym/s with a root-raised-cosine filter α = 0.35. The measured occupied bandwidth is close to the expected value, but the demodulator reports EVM = 18% and BER = 2×10⁻⁵ at an Eb/N0 that should give near 10⁻⁶.
474 words, about 2 min5Phase Margin and Settling Trade-Off With a Capacitive Load
A unity-feedback op-amp loop is intended for a 1.5 MHz crossover with 60° phase margin. On the bench, the loop has fc = 1.50 MHz but phase margin only 18°.
480 words, about 2 min