Phase Margin and Settling Trade-Off With a Capacitive Load
A unity-feedback op-amp loop is intended for a 1.5 MHz crossover with 60° phase margin. On the bench, the loop has fc = 1.50 MHz but phase margin only 18°. A 100 pF capacitive load is driven directly; the op-amp output resistance is 800 Ω. The step response shows 45% overshoot and about six cycles of ringing. The gain-bandwidth product is 10 MHz, and the slew rate is 20 V/µs. The team can add an isolation resistor, a feedback capacitor, or reduce the closed-loop bandwidth. The output must settle to 0.1% in 1 µs for a 1 V step, and the load capacitance cannot be removed. The supply is ±5 V and the output swing is 0 to 2 V.
1. Assess the stability from the phase margin and explain the observed overshoot and ringing.
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A phase margin of 18° is far below the intended 60° and indicates a heavily underdamped closed-loop response. For a second-order loop, low phase margin corresponds to low damping: PM ≈ 18° implies ζ of roughly 0.15–0.2, which predicts overshoot well above 45% and many cycles of ringing. The measured 45% overshoot and six cycles are therefore consistent with the low PM, even if the exact overshoot differs because of higher-order poles and zeros. The loop is not oscillating, but it has insufficient margin for reliable settling and for component tolerances.
2. Estimate the phase lag contributed by the capacitive load and judge whether it is a credible cause.
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The output resistance and load capacitance form a pole at fp = 1/(2πRoCL) = 1/(2π × 800 Ω × 100 pF) ≈ 1.99 MHz. At the 1.50 MHz crossover, this pole contributes a phase lag of arctan(1.50/1.99) ≈ 37°. That is a large fraction of the missing phase margin and is a credible contributor to the drop from 60° to 18°. The op-amp's own high-frequency poles add further lag, so the load pole alone does not have to account for the entire deficit. Directly driving 100 pF without isolation is therefore a poor design choice for this crossover frequency.
3. Recommend a compensation approach and check it against the 1 µs, 0.1% settling requirement.
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Do not simply reduce the closed-loop bandwidth. For first-order settling to 0.1%, e^(−t/τ) = 0.001 gives t/τ ≈ 6.91, so τ ≤ 1 µs/6.91 = 0.145 µs and the closed-loop bandwidth must be at least about 1/(2πτ) ≈ 1.10 MHz. Reducing fc to 0.8 MHz would miss the settling requirement. Instead, add an isolation resistor between the op-amp output and CL, with a feedback capacitor across the resistor if needed, to create a zero that counteracts the load pole; a resistor on the order of 1 kΩ places the zero near the crossover for 100 pF, but verify load regulation and output swing. Alternatively, use an internally compensated op-amp rated for the load. Re-simulate PM, overshoot, and 0.1% settling, including tolerances, before accepting the fix.