Kerala Plus Two Electronics (DHSE) common mistakes
Kerala Plus Two Electronics (DHSE) · Understand the traps and how to avoid them.
When asked to find the Q-point of a BJT bias circuit, the candidate writes V_CE = V_CC − I_C R_C and stops, ignoring the emitter resistor drop (or treats V_BE as 0.7 V but forgets I_E ≈ I_C when computing the emitter voltage).
Textbook derivations for fixed bias are memorised as a single formula; the candidate pattern-matches the circuit to the nearest remembered equation instead of writing the collector-emitter loop for the actual circuit drawn.
What to do instead
Always write the full loop equation for the specific circuit: V_CC = I_C R_C + V_CE + I_E R_E, then substitute I_E ≈ I_C. Practise three bias types (fixed, collector-to-base, voltage-divider with and without bypass) from the loop equation each time rather than from a formula sheet, and check the result against the saturation current V_CC/(R_C + R_E).
The candidate labels the zener diode as forward biased in a shunt regulator and predicts the output as V_Z + 0.7 V, or claims the zener regulates when the input falls below V_Z.
Confusion between the two operating regions of a diode; the reverse-breakdown behaviour of the zener is learned as a number (V_Z) without the condition 'reverse biased and above V_Z'.
What to do instead
State the two conditions explicitly before calculating: the zener must be reverse biased and V_in (after the series resistor divider) must exceed V_Z. Draw the reverse characteristic with the breakdown knee and mark the regulation window; then solve one numerical case where V_in drops below V_Z and show the output simply follows the input minus the drop.
In a half-wave or full-wave rectifier numerical, the candidate uses the peak voltage as the DC output, or computes ripple frequency as f for a bridge rectifier instead of 2f.
Peak, RMS and average values of a sinusoid are mixed up, and the doubling of ripple frequency in full-wave circuits is memorised as a phrase rather than derived from the number of pulses per cycle.
What to do instead
For every rectifier problem, first sketch the output waveform and count the pulses per input cycle. Then apply V_dc = 2V_m/π (full-wave) or V_m/π (half-wave) with V_m = √2 V_rms, and subtract the diode drops (two drops for a bridge). Verify with a worked example at 50 Hz where the ripple must come out as 100 Hz.
When calculating the voltage gain of a CE amplifier, the candidate substitutes the DC collector resistor R_C for the AC load, ignoring r_L = R_C ∥ R_L, and omits the emitter bypass effect on gain.
DC and AC equivalent circuits are not separated; the candidate works from the schematic values directly instead of redrawing the AC equivalent with capacitors shorted and supplies grounded.
What to do instead
Adopt a fixed two-step routine: draw the DC circuit (capacitors open) for the Q-point, then a separate AC equivalent (capacitors short, V_CC to ground) for gain. Compute A_v = −(r_L/r_e) with r_e = 26 mV/I_E, and note that an unbypassed R_E reduces gain to roughly −r_L/(r_e + R_E). Do at least one problem both with and without the bypass capacitor.
The candidate states that a transistor oscillator needs only an amplifier and feedback, without checking the Barkhausen condition, and cannot say why the feedback network must be frequency selective.
The oscillator is studied as a block diagram with the condition memorised as 'loop gain = 1' but not applied to a concrete circuit such as an RC phase-shift or Hartley oscillator.
What to do instead
For each oscillator type, write the feedback fraction β explicitly (1/29 for a three-section RC phase-shift network, L2/L1 for Hartley, C1/C2 for Colpitts) and verify Aβ = 1 at the design frequency with a 180° phase shift from the network. Practise computing the required gain and hence the minimum h_fe of the transistor.
When simplifying a Boolean expression or designing a combinational circuit, the candidate stops at a correct but non-minimal expression, or builds a circuit that works for the given truth table but has a static hazard or unused gate inputs left floating.
The answer is checked only by testing the input combinations in the question rather than by Karnaugh-map minimisation, and practical wiring rules for CMOS/TTL inputs are treated as separate theory rather than part of the design.
What to do instead
Always finish by plotting the K-map, grouping in powers of two, and comparing gate count with the algebraic result. Then apply the wiring checks: tie unused CMOS inputs to V_DD or ground, never leave them open, and add a redundant group in the K-map to remove the hazard when two groups are adjacent.
The candidate computes the bit rate and bandwidth of an AM or FM system using the same formula, for example applying BW = 2f_m to FM or forgetting the two sidebands when stating the bandwidth of AM.
Modulation index, sideband and deviation are learned as separate definitions without a single picture of the spectrum, so the formulas are recalled by name rather than from the spectrum.
What to do instead
Draw the spectrum for each case before substituting numbers: AM with carrier plus upper and lower sidebands gives BW = 2f_m; FM with modulation index m_f = Δf/f_m gives BW ≈ 2(Δf + f_m) by Carson's rule. Compute one numerical example for each and check that the sideband power of AM adds to P_total = P_c(1 + m²/2).
In an 8051 question the candidate mixes up the register banks, stack pointer behaviour and port pin structure, for example claiming all four ports have identical internal pull-ups or that the stack grows upward from 07H.
The 8051 architecture is memorised as a list of special function registers without a memory map, so addresses and reset values are recalled loosely.
What to do instead
Redraw the internal RAM map once by hand: bank 0–3 in 00H–1FH, bit-addressable area 20H–2FH, stack from 07H upward, and note that Port 0 needs external pull-ups while Ports 1–3 have internal ones. For each program, trace the SP value instruction by instruction on paper before answering.
When asked how to measure the voltage across a high-value resistor in a circuit, the candidate connects the voltmeter in series or ignores the meter's own resistance; when a bridge rectifier output is faulty, the candidate replaces components at random instead of testing the diodes.
The voltmeter and ammeter connection rules are learned as definitions without the loading effect, and troubleshooting is approached as component swapping rather than as a signal-tracing procedure.
What to do instead
Apply the connection rule first (voltmeter in parallel, ammeter in series, always start on the highest range) and then estimate loading: a 10 MΩ voltmeter across 1 MΩ is acceptable, a 20 kΩ/V meter is not. For faults, follow a fixed sequence: measure the AC input, the transformer secondary, the DC output, then check each diode with the multimeter diode test in both directions and record the readings.
In the practical record or viva, the candidate reports a measured gain or frequency that does not match the calculated value and offers no explanation, or draws the circuit diagram with the supply rails and pin numbers omitted so the wiring cannot be reproduced.
The laboratory work is treated as a ritual to obtain 'expected' readings rather than as a measurement with tolerances, and the record is copied from a guide without the drawing conventions that make a schematic buildable.
What to do instead
In every experiment, tabulate calculated and measured values side by side and state the likely cause of any deviation (component tolerance, meter loading, supply sag). Draw schematics with pin numbers, supply values and ground symbols, and before submission check that another student could rebuild the circuit from the diagram alone.