Digital Electronics and Logic Circuits
Digital Electronics and Logic Circuits tests number systems, Boolean algebra, universal gates, combinational blocks, flip-flops, counters and memory. DHSE problems often require simplification, truth-table completion or identifying a flip-flop or counter from its behaviour.
Core concepts
- Number systems: binary, octal and hexadecimal conversions; 2’s complement represents signed numbers; BCD uses four bits per decimal digit and has six invalid codes.
- Gates and universality: NAND and NOR can implement any logic function. De Morgan’s laws:
(A·B)' = A' + B'and(A + B)' = A'·B'. - Boolean simplification: use SOP/POS forms and Karnaugh maps; group 1s in sizes of 1, 2, 4 or 8, including edge wrapping, to remove redundant variables.
- Combinational circuits: half adder
S = A⊕B,C = AB; full adder adds carry-in; multiplexer selects one of many inputs; demultiplexer routes one input to many outputs; encoder and decoder convert codes. - Sequential circuits: SR latch, JK flip-flop (race-around problem), D and T flip-flops; edge triggering; registers store bits; ripple counters are asynchronous, synchronous counters clock all stages together; mod-N counters reset after N states.
- Memory: RAM is volatile; ROM is non-volatile; PROM, EPROM, EEPROM and flash differ in reprogrammability.
Worked example
Simplify Y = AB + A(B + C) + B(B + C). Expand: Y = AB + AB + AC + BB + BC. Since BB = B, this becomes AB + AC + B + BC. Factor: B(A + 1 + C) + AC. Because A + 1 + C = 1, Y = B + AC. This is shorter and uses fewer gates.
Traps that cost marks
- Forgetting the sign bit in 2’s complement or misreading the MSB.
- Applying De Morgan’s law without changing the operation sign.
- Missing K-map edge groupings or grouping an odd number of cells.
- Confusing a latch (level-triggered) with a flip-flop (edge-triggered).
- Leaving unused CMOS inputs floating instead of tying them to a defined level.