Contact Bounce and False Counts on a Conveyor Counter
A workshop project counts parts on a conveyor using an IR reflective sensor whose output goes low when a part passes. The signal is fed to the clock input of a 74LS90 decade counter, and its BCD output drives a 74LS47 decoder with a common-anode 7-segment display through 330 Ω resistors. On the first trial the display counts 3 to 5 times for each single part, and occasionally jumps to an unrelated digit when a fluorescent lamp starts. A DMM shows the sensor output resting at 3.2 V, falling to 0.4 V for 20 ms per part, with a 2 ms burst of ringing at both edges. The 5 V supply comes from a 7805 with 1000 µF at the input and 100 µF at the output, located 600 mm away on a separate board. The student has 74LS14 Schmitt inverters, 10 kΩ and 1 kΩ resistors, 100 nF capacitors, and a 74LS00.
1. Explain why one part produces several counts and why the lamp start causes a false digit. Propose a debounce/interface circuit with component values and justify the time constant.
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The 74LS90 counts negative edges. The sensor edge is slow (20 ms fall) and has 2 ms ringing, so as the signal passes the TTL threshold several times the counter sees several clock edges; a single part can therefore add 3–5 counts. The 3.2 V high level is only 1.2 V above the 2.0 V VIH of LS TTL, so lamp-induced noise can also cross the threshold and produce a false count. Add a 1 kΩ pull-up from the sensor output to +5 V to raise the high level and lower the source impedance. Then pass the signal through an RC low-pass (10 kΩ, 100 nF, τ = 1 ms, fc ≈ 160 Hz) followed by a 74LS14 Schmitt inverter; the Schmitt hysteresis of about 0.8 V cleans the slow edge, and the RC attenuates the 2 ms ringing. The 1 ms time constant is short compared with the 20 ms pulse, so the count is not missed, but long enough to suppress the ringing. Feed the cleaned edge to the 74LS90 clock, using two inverter stages if the required edge polarity is reversed. Add 100 nF at the 74LS90 and 74LS47 supply pins and a 100 µF local reservoir, because the 7805 is 600 mm away.
2. Check the DC fan-out if each of the four 74LS90 BCD outputs drives the 74LS47 and two 74LS00 inputs. Use LS-TTL input currents I_IL = 0.4 mA and I_IH = 20 µA, and output limits I_OL = 8 mA and I_OH = 0.4 mA. Is direct connection safe?
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Each BCD line drives the 74LS47 plus two 74LS00 inputs, i.e. three LS inputs per line. In the low state, each input sinks 0.4 mA, so the total is 3 × 0.4 = 1.2 mA. The 74LS90 output can sink 8 mA, so the load is only 1.2/8 = 15% of the limit; this is safe. In the high state, each input draws 20 µA, so the total is 60 µA against a 400 µA output source limit; this is also safe, with a fan-out margin of about 6.7. However, the 74LS47 blanking and ripple-blanking pins must be tied to the correct levels, and the display series resistors must suit common-anode wiring. The more serious issue is noise margin: the 3.2 V sensor high is marginal, but the 74LS90 outputs are standard LS levels. Keep the decoupling capacitors close and avoid long unshielded runs. If a fourth LS input were added, the low-state load would be 1.6 mA, still safe, but the high-state sum would be 80 µA; the practical limit is usually set by capacitive loading and noise, not DC fan-out.