Maharashtra HSC Electronics Technology (Vocational) cheat sheet

Diode equation: I = Is(e^(V/(nVT)) − 1), with VT ≈ 26 mV at room temperature; barrier potential is about 0.7 V for silicon and 0.3 V for germanium.

Forward bias means anode positive to cathode: the depletion region narrows and conduction current flows; reverse bias widens it and only leakage (µA) flows.

Ordinary rectifier diodes are destroyed by reverse breakdown; zener diodes are doped to break down safely and hold a near-constant voltage for regulation.

BJT current relations: IE = IC + IB, IC = βIB, α = IC/IE = β/(β+1); β typically 50–300 and rises with temperature.

BJT operating regions: cutoff (both junctions reverse) for OFF switching, active (BE forward, CB reverse) for amplification, saturation (both forward) for ON switching.

MOSFET is voltage controlled: enhancement-mode n-channel conducts only when VGS > Vth, and the gate draws negligible steady-state current because of the oxide insulation.

Doping rule: pentavalent donors (phosphorus, arsenic) make n-type; trivalent acceptors (boron, aluminium) make p-type; majority carriers determine conduction type.

LED series resistor: R = (Vsupply − Vf)/If, then pick the next higher standard value; Vf ≈ 1.8–2.2 V red, 3.0–3.4 V blue/white.

Colour code digits: black 0, brown 1, red 2, orange 3, yellow 4, green 5, blue 6, violet 7, grey 8, white 9; gold band = ±5 %, silver = ±10 %, no band = ±20 %.

Resistors: series R = R1 + R2 + …; parallel 1/R = Σ(1/Ri); for two resistors in parallel R = (R1R2)/(R1 + R2).

Capacitors combine opposite to resistors: parallel values add, series values follow reciprocals. Inductors combine like resistors.

Reactance: XC = 1/(2πfC) and XL = 2πfL; series resonance at f0 = 1/(2π√(LC)), where XL = XC, Z = R (minimum) and current peaks.

RC charging: v(t) = V(1 − e^(−t/RC)); one time constant reaches 63.2 %, five time constants 99.3 %.

Tolerance decision rule: a ±5 % 10 kΩ part may sit anywhere in 9.5–10.5 kΩ, so use ±1 % metal-film types where gain, timing or bridge balance depends on the value.

Potentiometer wiring: as a two-terminal rheostat it varies current; as a three-terminal divider it taps a fixed fraction of the applied voltage.

Energy storage: a capacitor opposes change of voltage (W = ½CV²) and an inductor opposes change of current (W = ½LI²).

Transformer relation: Vs/Vp = Ns/Np; a step-down transformer lowers mains to the required AC level and isolates the low-voltage side.

Half-wave rectifier: one diode, ripple factor 1.21, efficiency 40.6 %, PIV = Vm, output ripple frequency equal to the supply frequency.

Full-wave centre-tap: two diodes, ripple factor 0.48, efficiency 81.2 %, PIV = 2Vm, ripple frequency = 2 × supply frequency.

Bridge rectifier: four diodes, ripple factor 0.48, PIV = Vm, ripple frequency = 2f, and no centre-tapped transformer is needed.

Filter sizing (full-wave): C ≈ Iload/(2f × Vripple); a larger capacitor cuts ripple but raises peak diode and transformer surge current.

78xx/79xx series: fixed positive/negative three-terminal regulators; input must exceed output by roughly 2 V dropout, with 0.33 µF at input and 0.1 µF at output.

Linear vs SMPS decision: linear is simple and low-noise but dissipates (Vin − Vout) × I as heat; a switcher is efficient but needs filtering for EMI and ripple.

Fuse selection: typically 1.5–2 × normal operating current, slow-blow for motors and inductive loads that draw inrush current.

Decibel formulas: voltage gain (dB) = 20 log(Vout/Vin), power gain (dB) = 10 log(Pout/Pin); the −3 dB point is half power, i.e. 0.707 of the voltage.

CE amplifier: high voltage gain, moderate input impedance, low output impedance-ish and 180° phase inversion; CC (emitter follower) gives gain ≈ 1 with high input and low output impedance for buffering.

CB amplifier: very low input impedance, high output impedance, no phase inversion, and the best high-frequency response of the three configurations.

Class A conducts 360°, maximum efficiency 25 % (resistive load) or 50 % (transformer-coupled), lowest distortion; class B conducts 180° with 78.5 % maximum efficiency and crossover distortion.

Class AB slightly forward-biases the output devices to remove crossover distortion; class C conducts under 180°, exceeds 80 % efficiency and needs a tuned RF load.

Barkhausen criterion: loop gain ≥ 1 and total loop phase shift of 0° or 360° at the oscillation frequency; RC phase-shift oscillators use three 60° sections.

Colpitts uses a tapped capacitive divider and Hartley a tapped inductive divider in the tank; crystal oscillators use piezoelectric resonance for very high Q and stability.

Op-amp closed-loop gains: inverting = −Rf/Rin, non-inverting = 1 + Rf/Rin; slew-rate limit gives maximum undistorted frequency fmax = SR/(2πVp).

De Morgan: (A·B)' = A' + B' and (A + B)' = A'·B'; a NAND behaves as a bubbled OR and a NOR as a bubbled AND.

NAND and NOR are universal gates - any combinational function can be implemented using either type alone.

XOR outputs 1 only when inputs differ; it provides the sum bit of a half adder and the parity bit in data transmission.

Half adder: Sum = A ⊕ B, Carry = A·B; a full adder adds three inputs using two half adders plus an OR gate.

SR latch has a forbidden state when both inputs are active; the JK flip-flop removes it by toggling when J = K = 1, and the D flip-flop simply captures D on the clock edge.

n flip-flops give a maximum modulus of 2^n; ripple (asynchronous) counters accumulate propagation delay, so synchronous counters are used at high frequency.

Karnaugh map rule: group 1, 2, 4 or 8 adjacent cells (powers of two, wrapping at edges); each group eliminates one variable per doubling of size.

ADC resolution = Vref/2^n; a 10-bit converter with a 5 V reference resolves 5/1024 ≈ 4.88 mV per step, and each extra bit halves the step size.

AM bandwidth = 2fm; modulation index m = Vm/Vc, and m > 1 means overmodulation with envelope distortion and sideband splatter.

FM uses constant amplitude and carries information in frequency deviation; Carson's rule gives bandwidth ≈ 2(Δf + fm).

Nyquist criterion: fs ≥ 2 × fmax, otherwise aliasing folds high frequencies onto low ones; an anti-alias low-pass filter is placed before the sampler.

PCM chain = sampling → quantising → encoding; bit rate = fs × n bits/s, and SNR improves about 6 dB for each additional quantising bit.

Shannon–Hartley: C = B log2(1 + S/N) bit/s; capacity is linear in bandwidth but only logarithmic in signal-to-noise ratio.

Power in dBm: P(dBm) = 10 log(P/1 mW); 0 dBm = 1 mW, +3 dBm ≈ 2 mW, and −3 dB is half power.

Trade-off rule: FM and PSK resist amplitude noise better than AM, while higher-order QAM raises bit rate per hertz at the cost of tighter SNR requirements.

Antenna length: λ = c/f, so a half-wave dipole is λ/2 long - roughly 1.5 m at 100 MHz and 0.15 m at 1 GHz.

Classic 8051 core: 8-bit CPU, 4 KB on-chip program ROM, 128 bytes RAM, four register banks of eight registers, 32 I/O lines on ports P0–P3, and two 16-bit timers.

Key SFRs: ACC, B, PSW, SP, DPTR, P0–P3, TMOD, TCON, SCON, SBUF, IE, IP; the PSW carries the carry, auxiliary carry, overflow and register-bank select bits.

Timer clock = crystal frequency/12; at 12 MHz one count = 1 µs, and mode-1 reload value = 65536 − required count.

Interrupt sources are external 0/1, timer 0/1 and serial; IE enables them individually, IP sets priority, and every ISR must end with RETI.

Serial port mode 1 is 8-bit UART with a start bit, eight data bits and a stop bit; SCON selects the mode and timer 1 usually generates the baud rate.

Harvard architecture: program (code) and data (RAM) memory spaces are separate, so code and data addresses do not overlap.

Watchdog timer resets the CPU if firmware fails to clear it within the timeout, recovering the system from a hang or infinite loop.

Key debounce: a 10–20 ms software delay or an RC filter after the switch, since mechanical contacts bounce for several milliseconds.

CRO reading: amplitude = vertical divisions × volts/div, period = horizontal divisions × time/div, and f = 1/T; use the ×10 probe for high impedance and lower loading.

Compensate a ×10 probe against the calibrator square wave before measuring, adjusting the trimmer until the corners are square, not rounded or peaked.

Loading error: a voltmeter of resistance Rm across a source resistance Rs reads low by the factor Rm/(Rm + Rs), so Rm must be far greater than Rs.

Ammeter rule: low resistance, connected in series; a voltmeter has high resistance and is connected in parallel - connecting an ammeter across a supply shorts it.

Accuracy versus precision: accuracy is closeness to the true value, precision is repeatability; error % = (measured − true)/true × 100.

Wheatstone bridge balances when R1/R2 = R3/R4; at balance no current flows through the galvanometer and the unknown arm can be calculated from the ratio arms.

Resistance measurement: switch off and isolate the component before using an ohmmeter, otherwise parallel paths and residual voltage corrupt the reading.

Level reference: 0 dBm = 1 mW, which is 0.224 V RMS across 50 Ω and 0.775 V RMS across 600 Ω.

Solder alloys: 63/37 SnPb is eutectic at 183 °C; lead-free SAC305 melts near 217–220 °C, so iron tips run about 300–350 °C for leaded and 350–380 °C for lead-free work.

Flux removes surface oxide and aids wetting; rosin mildly activated flux suits hand assembly, and residues must be cleaned where the design demands it.

Acceptable joint: smooth concave fillet with visible wetting to pad and lead; a dull, grainy, convex joint is cold and must be reflowed with fresh flux and heat.

Trace width rule of thumb for 1 oz outer-layer copper: about 1 mm per 1 A, with wider traces and copper pours for power and ground returns.

Clearance and creepage: keep at least 0.2–0.3 mm between low-voltage traces, and several millimetres of creepage between mains and low-voltage circuitry at 230 V.

Board layers: silkscreen legend, solder mask openings over pads only, copper foil, and FR-4 substrate; vias connect layers and need an annular ring around the drill.

ESD control: earthed wrist strap through a 1 MΩ resistor, grounded soldering iron tip, and CMOS devices stored in conductive foam or antistatic tubes.

Desoldering: add fresh solder and flux, then use a solder sucker or wick; limit heat on each pad to a few seconds to avoid lifting pads and delaminating the board.