Digital Electronics and Logic Circuits
Digital Electronics and Logic Circuits tests number systems, Boolean simplification, gate behaviour, combinational blocks, flip-flops, counters, and logic-family characteristics. Expect truth tables, K-maps, and timing definitions.
Core rules
- De Morgan: (A·B)′ = A′ + B′ and (A + B)′ = A′·B′. NAND and NOR are universal gates.
- A K-map groups 1s in powers of two; larger groups give simpler terms. Don’t-care cells may be grouped for simplification.
- Combinational outputs depend only on present inputs; sequential outputs depend on present inputs and stored state.
- A D flip-flop samples D at the clock edge; setup and hold times must be met or metastability can occur.
- An n-bit binary counter has 2^n states; a modulo-N counter needs enough flip-flops for 2^n ≥ N.
- CMOS draws little static current but significant dynamic current at high frequency; unused CMOS inputs must not float.
Worked example
Simplify F = Σm(0,1,2) for variables A,B, where minterms are A′B′, A′B, AB′. Group m0 with m1: they differ only in B, giving A′. Group m0 with m2: they differ only in A, giving B′. Therefore F = A′ + B′. Check A=0,B=0: both terms true, F=1; A=1,B=1: both false, F=0, matching the minterm list.
Traps
Confusing XOR with OR: XOR is 1 only when inputs differ. Ignoring active-low signals inverts enable/reset logic. Treating asynchronous clear as clocked causes timing errors. In K-maps, wrapping edges is valid but diagonal grouping is not. Floating TTL inputs tend to read high, while floating CMOS inputs can oscillate and waste power.