Microcontrollers and Embedded Fundamentals
Microcontrollers and Embedded Fundamentals tests architecture, memory maps, GPIO, timers, interrupts, ADC, serial buses, and basic embedded C. Expect register-level reasoning and resource calculations.
Core rules
- Harvard architecture has separate program and data memories; von Neumann shares one address space.
- GPIO direction and data registers must be configured; a floating input needs a pull-up or pull-down.
- Polling checks a flag repeatedly; interrupts let an ISR run on an event. Keep ISRs short and use volatile for shared flags.
- Timer delay depends on clock, prescaler, and counter modulus: delay = (prescaler × counts)/fclock.
- An n-bit ADC has 2^n codes and resolution Vref/2^n; for a 5 V, 8-bit ADC, one code ≈ 19.6 mV.
- UART is asynchronous and frame-based; SPI is full-duplex with chip select; I²C uses two wires and addresses.
- A watchdog timer resets a hung system unless the firmware services it.
Worked example
An 8-bit ADC has Vref = 5.0 V and output code 200. Using the common code-to-voltage relation Vin = code × Vref/(2^8 − 1), Vin = 200 × 5/255 = 3.92 V. The step size is 5/255 ≈ 19.6 mV, so the result is about 3.92 V ± half a step. If the datasheet defines full-scale as 256 steps, use 256 and state the convention.
Traps
Using 256 instead of 255 without checking the datasheet changes the answer. Forgetting to set a pin as output makes it appear dead. Long calculations inside an ISR cause missed interrupts. Ignoring switch bounce produces multiple counts. A UART baud-rate error beyond a few percent causes framing errors.