Common-Emitter Stage That Clips Despite a 'Perfect' Q-Point
A common-emitter amplifier is built with VCC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, RC = 2.2 kΩ and RE = 1 kΩ, with RE bypassed by a 100 µF capacitor. The transistor data sheet gives hFE between 100 and 300 at IC = 1–2 mA, VBE ≈ 0.7 V and VA = 100 V. The builder measures VB = 2.05 V, VE = 1.35 V and VCE = 7.5 V with hFE ≈ 120, and considers the bias "textbook perfect". A 10 kΩ load is then AC-coupled to the collector, and a 50 mV peak, 1 kHz sine is applied at the input through a coupling capacitor. The oscilloscope shows a clean sine on one half-cycle and a flat top on the other, and the builder proposes simply raising VCC to 20 V to "get the swing back".
1. Compute the quiescent collector current for hFE = 100 and hFE = 300 and decide whether bias stability is the problem.
Read the worked answer
Thevenin equivalent of the divider. VBB = 12 × 10/(47 + 10) = 2.105 V; RB = 47k‖10k = 8.25 kΩ.
Emitter current. IE = (VBB − VBE)/(RE + RB/(hFE + 1)).
- hFE = 100: IE = (2.105 − 0.7)/(1000 + 81.7) = 1.405/1081.7 = 1.30 mA
- hFE = 300: IE = 1.405/(1000 + 27.4) = 1.37 mA
IC ≈ IE, so the collector current moves by only about 5% over a 3:1 spread in hFE, and VCE = 12 − IC(RC + RE) gives 7.8 V and 7.6 V respectively, matching the measured 7.5 V.
Verdict: the bias is genuinely stable. The reason is that RE = 1 kΩ is much larger than the worst-case base-path resistance RB/(hFE + 1) = 82 Ω, so the emitter sets the current and β barely matters. Bias drift is therefore not the cause of the distortion; the fault must lie in the signal-swing budget, which the next calculation exposes.
2. Calculate the small-signal voltage gain with the 10 kΩ load and the maximum unclipped output swing. Explain which half-cycle flattens and why.
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Small-signal parameters. re = 26 mV/IE = 26 mV/1.35 mA ≈ 19 Ω. The AC collector load is rc = RC‖RL = 2.2k‖10k = 1.80 kΩ.
Gain. With RE fully bypassed, Av ≈ rc/re = 1800/19 ≈ 95 (including VA would lower this only slightly). A 50 mV peak input therefore demands 4.75 V peak at the collector.
Swing available. The transistor cuts off when the instantaneous collector current reaches zero, so the output can rise by only ICQ × rc = 1.35 mA × 1.80 kΩ = 2.43 V above its quiescent point. Downward it can fall to VCEQ − VCE(sat) ≈ 7.5 − 0.3 = 7.2 V, which is not the limit.
Diagnosis. The stage clips at 2.43 V peak, not 4.75 V, so any input above about 2.43/95 = 26 mV peak flattens. Because the output rises when the input falls, the positive-going output - the negative input half-cycle - is the one with the flat top. This is cutoff clipping caused by too much gain for the available current swing, not by the supply rail.
3. Evaluate the proposal to raise VCC to 20 V, and recommend a change that actually removes the clipping.
Read the worked answer
Why 20 V does not help. The divider ratio is unchanged, so VBB scales to 3.51 V and ICQ stays at about 1.35 mA. VCEQ becomes 20 − 1.35 × 3.2 = 15.7 V, which only adds unused voltage between the transistor and ground. The upward swing limit is still ICQ × rc = 2.43 V, because cutoff depends on the current reaching zero, not on the supply voltage. The amplifier would run hotter, need a larger VCC decoupling capacitor, and clip at exactly the same input level. The proposal treats the symptom (rail headroom) rather than the cause (excess gain).
What does work.
- Reduce gain by leaving part of RE unbypassed: with 100 Ω unbypassed, Av ≈ 1800/(19 + 100) ≈ 15, so 50 mV peak gives 0.75 V, well inside the 2.43 V ceiling.
- Or attenuate the input to below 26 mV peak with a resistive pad ahead of the coupling capacitor.
- Or redesign the Q-point for a symmetric swing by raising ICQ to VCC/(RC + RE + rc) ≈ 2.4 mA and readjusting R1/R2; this gives about 4.3 V of swing, but gain rises to ≈167, so the 50 mV input still has to be attenuated.
For a 50 mV source the honest answer is that the stage has roughly 11 dB too much gain; fixing the bias alone cannot solve it.