Tamil Nadu HSE Second Year Basic Electronics Engineering common mistakes
Tamil Nadu HSE Second Year Basic Electronics Engineering · Understand the traps and how to avoid them.
Stating that a forward-biased PN junction has a wide depletion layer and high resistance, or that reverse bias narrows the depletion region, instead of the opposite.
Candidates memorise the words 'forward' and 'reverse' as labels on a diagram without linking them to the physics: forward bias pushes majority carriers toward the junction and shrinks the depletion layer, lowering the barrier potential (about 0.7 V for silicon, 0.3 V for germanium); reverse bias widens it and raises the barrier. The confusion is reinforced because reverse bias produces a large voltage but a tiny current, which feels contradictory.
What to do instead
Before answering, sketch the junction and write the barrier value beside it. For every bias question, state three quantities in order: depletion width, barrier potential, and resistance. Forward = narrow, low barrier, low resistance; reverse = wide, high barrier, high resistance. Then check the answer against the diode current equation I = I0(e^(V/nVT) − 1), which predicts exponential rise only for positive V.
Calculating the Q-point of a BJT bias circuit using the wrong base current path, for example treating a voltage-divider bias as if the divider were unloaded or forgetting VBE in the base loop.
Candidates apply KVL to the base-emitter loop but drop the 0.7 V drop, or they use the full divider voltage as base voltage without checking whether the divider current is much larger than IB. When the approximation fails, the calculated IC and VCE are wrong and the transistor may be reported as saturated when it is actually active.
What to do instead
Always write the loop explicitly: VBB = IB·RB + VBE + IE·RE, with IE = (β+1)IB. Verify the divider approximation by checking that the divider current is at least ten times IB; if not, solve the Thevenin equivalent of the divider (VTH and RTH) and use VTH = IB·RTH + VBE + IE·RE. Finally test the result: if VCE comes out below about 0.2 V, declare saturation and redo with VCE(sat).
Confusing JFET and MOSFET behaviour, such as claiming a JFET can be biased with either gate polarity, or that an enhancement MOSFET conducts at VGS = 0.
The transfer characteristics look similar on a graph, so candidates transfer rules from one device to the other. They forget that a JFET gate junction must stay reverse biased (so VGS has one allowed polarity for an n-channel device), while an enhancement MOSFET needs VGS above the threshold VT to form the channel.
What to do instead
Build a one-line comparison for each device: n-channel JFET, VGS between VGS(off) and 0, ID = IDSS(1 − VGS/VGS(off))²; depletion MOSFET, both polarities allowed; enhancement MOSFET, VGS > VT only, ID = k(VGS − VT)². For every problem, first identify the device type and channel, then write the correct square-law equation before substituting numbers.
Applying the ideal op-amp rules (zero differential input voltage, zero input current) to a circuit that is operating in saturation, or to a comparator, and then reporting a linear output.
The virtual-short and virtual-open rules only hold when negative feedback keeps the amplifier in its linear region. Candidates apply them mechanically to open-loop comparators, Schmitt triggers, and oscillators, where the output is clipped at the supply rails, and they produce answers like Vout = 5 V from a gain formula when the real output is +12 V or −12 V.
What to do instead
Before using virtual short, confirm two things: negative feedback exists from output to inverting input, and the computed output lies within the supply rails. If either check fails, set the output to the appropriate rail and analyse the input crossing instead. For comparator and Schmitt trigger questions, always state the reference voltage and the two threshold levels explicitly.
Simplifying Boolean expressions with Karnaugh maps but leaving out the don't-care or wrap-around adjacencies, or converting a truth table to a logic circuit without minimising, so the answer is logically correct but not the expected minimal form.
Candidates group only obvious horizontal pairs and miss the four-corner grouping and the top-bottom, left-right wrap-around. They also treat X (don't-care) entries as zeros, which blocks valid larger groupings and yields a longer expression than the examiner expects.
What to do instead
Follow a fixed routine: mark all 1s, then all Xs, then look for the largest possible group (8, then 4, then 2) starting from each 1, using wrap-around edges and corners. Treat X as 1 only when it enlarges a group. After minimising, expand the result back to verify it covers every 1 in the original truth table.
Mixing up the truth tables and output states of flip-flop types, for example giving the JK flip-flop a forbidden state or saying a D flip-flop toggles when D is held high.
The SR latch's invalid state (S = R = 1) is memorable, and candidates carry it over to JK, where the same input combination is deliberately defined as toggle. Similarly, the D flip-flop is described as 'following the input' without noting that the output only changes at the clock edge.
What to do instead
Write out the four-row characteristic table for each flip-flop and memorise the distinguishing row: SR has an invalid row, JK has toggle, T has toggle, D simply copies. Then attach the clock condition: latch is level-sensitive, flip-flop is edge-triggered. Practise drawing the output waveform for a given clock and input sequence, marking each active edge.
Calculating modulation index or sideband power for AM with the wrong formula, such as using m = (Vmax − Vmin)/Vmax, or forgetting that total power includes the carrier.
The two equivalent expressions for AM modulation index, m = Vm/Vc and m = (Vmax − Vmin)/(Vmax + Vmin), are easily half-remembered. Candidates also compute only the sideband power and forget the unmodulated carrier term, or apply the AM power formula to an FM question.
What to do instead
Write the standard results once and reuse them: m = (Vmax − Vmin)/(Vmax + Vmin), total power Pt = Pc(1 + m²/2), and sideband power = Pc·m²/2. Check plausibility: with m = 1, total power should be 1.5 times carrier power. For FM, use the modulation index β = Δf/fm and Bessel/Carson's rule instead, and state which modulation you are answering.
Treating an SCR as a normal diode that conducts in both directions, or claiming it turns off automatically when the gate signal is removed.
The gate is described as the control terminal, so candidates assume removing the gate pulse stops conduction, as with a transistor. In reality, once an SCR latches on, the gate loses control and conduction continues until the anode current falls below the holding current.
What to do instead
Memorise the three conditions for turn-off: anode current below holding current, reverse anode voltage, or a forced commutation circuit. For every SCR question, state the latching and holding current values and explain that the gate only triggers. Also distinguish the three terminals and the forward-blocking, forward-conduction, and reverse-blocking regions on the V-I curve.
Connecting an ammeter in parallel with a load or a voltmeter in series, or ignoring the loading effect of the instrument on the measurement.
Candidates learn 'ammeter in series, voltmeter in parallel' as a slogan but do not connect it to the reason: an ideal ammeter has zero resistance and an ideal voltmeter has infinite resistance. When the real resistances are finite, the meter changes the circuit and the reading differs from the true value, which candidates do not account for.
What to do instead
For each measurement, draw the meter into the circuit and label its internal resistance. Compute the loading error: for a voltmeter of resistance Rv across a source of resistance Rs, the error fraction is Rs/(Rs + Rv). If the error is significant, choose a higher-range voltmeter or apply the correction. Also state the instrument type (moving coil, moving iron, digital) and its effect on AC versus DC readings.
Writing 8051 assembly or C code that reads a port pin without first writing 1 to that pin, or that forgets to configure the port as input, so the program always reads the internal latch instead of the external signal.
The 8051 quasi-bidirectional ports have a weak internal pull-up and a latch that must be set high before the pin can be used as an input. Candidates who treat ports as simple direction-selectable pins, as on some other microcontrollers, omit the write-1 step and get a constant reading.
What to do instead
Adopt a fixed input routine: write 1 to the port bit (for example SETB P1.0), then read it with a MOV or JB instruction. For output, write the desired value and remember that the pin sinks current better than it sources. When answering code questions, annotate each port access with whether it is a read of the pin or of the latch.