Combinational and Sequential Logic Circuits
This domain separates circuits whose output depends only on present inputs from clocked circuits that store state.
Core concepts
- Combinational blocks: half and full adder, subtractor, multiplexer, demultiplexer, decoder, encoder, magnitude comparator.
- Full adder: Sum = A ⊕ B ⊕ C_in; C_out = AB + C_in(A ⊕ B). A 2^n-to-1 multiplexer needs n select lines.
- Sequential blocks remember: latches are level-triggered, flip-flops are edge-triggered. SR, JK, D and T types; T and J = K = 1 give the toggle (divide-by-2) action.
- Shift registers: SISO, SIPO, PISO, PIPO; a 4-bit SIPO converts serial to parallel in four clocks.
- Counters: ripple (asynchronous) counters are simple but delays accumulate; synchronous counters clock every stage together. An n-bit counter has modulus 2^n; a truncated modulus is produced by decoding and resetting (e.g. MOD-6 resets at 0110).
Worked example
A 4-bit ripple counter driven by an 8 kHz clock has modulus 16. The output of the last stage is the input frequency divided by 16: 8000/16 = 500 Hz. Each stage halves the frequency, so the outputs are 4 kHz, 2 kHz, 1 kHz and 500 Hz. To obtain MOD-10, decode 1010 (decimal 10) and clear the flip-flops.
Traps
Assuming ripple counters switch simultaneously (decoding glitches occur); forgetting that a MOD-N counter needs decoding at N, not N − 1; applying the toggle rule to a level-triggered latch; confusing a multiplexer's data inputs with its select lines.