ALU 101 cheat sheet

The ALU is a combinational block that performs arithmetic and bitwise logic operations on operands and outputs a result plus status flags.

Core status flags: Zero (Z, result all zeros), Carry (C, carry-out or borrow), Overflow (V, signed range exceeded), Negative/Sign (N, result MSB).

Overflow for signed addition occurs when two operands of the same sign produce a result of the opposite sign: V = C_in(MSB) XOR C_out(MSB).

Subtraction is implemented as A + (~B) + 1 using two's complement; the carry-out in this case is an active-low borrow.

ALU width N determines operand size; an N-bit ALU produces an N-bit result and drives flags from bit N-1 and the final carry.

A one-bit ALU cell typically contains a full adder plus a multiplexer selecting between AND, OR, XOR, and sum outputs.

Operation select lines (opcode) choose the ALU function; k select bits support up to 2^k distinct operations.

Flags are registered in a status register so later conditional branches can test them.

An n-bit unsigned integer represents values 0 to 2^n − 1; an n-bit two's complement integer represents −2^(n−1) to 2^(n−1) − 1.

Two's complement negation: invert all bits and add 1; the value 0 has a single representation, and the most negative value has no positive counterpart.

Sign extension replicates the MSB when widening a signed value; zero extension pads with 0s when widening an unsigned value.

Hexadecimal groups 4 bits per digit; octal groups 3 bits per digit; conversion between these and binary is positional.

IEEE 754 single precision: 1 sign bit, 8 exponent bits (bias 127), 23 fraction bits; value = (−1)^S × 1.F × 2^(E−127) for normalized numbers.

IEEE 754 double precision uses 1 sign bit, 11 exponent bits (bias 1023), and 52 fraction bits.

Ranges for 8-bit: unsigned 0–255, signed −128 to 127; 16-bit: unsigned 0–65535, signed −32768 to 32767.

A carry out of the MSB is discarded when the result width matches the operand width; only the retained n bits are the result.

Basic identities: A + 0 = A, A · 1 = A, A + 1 = 1, A · 0 = 0, A + A = A, A · A = A.

Complement laws: A + A' = 1, A · A' = 0, (A')' = A.

De Morgan's laws: (A + B)' = A' · B', and (A · B)' = A' + B'.

Distributive laws: A(B + C) = AB + AC and A + BC = (A + B)(A + C).

Absorption: A + AB = A and A(A + B) = A; consensus: AB + A'C + BC = AB + A'C.

NAND and NOR are functionally complete: any Boolean function can be built from NAND gates alone or NOR gates alone.

XOR: A ⊕ B = A'B + AB'; identities A ⊕ 0 = A, A ⊕ 1 = A', A ⊕ A = 0.

A minterm is a product term true for exactly one input combination; a maxterm is a sum term false for exactly one combination.

Combinational logic output depends only on current inputs; sequential logic output depends on inputs and stored state.

A D flip-flop captures D on the active clock edge; a D latch is level-sensitive and transparent while enable is asserted.

Setup time is the interval before the clock edge during which data must be stable; hold time is the interval after the edge.

Maximum clock frequency is bounded by t_clk ≥ t_clk-to-Q + t_comb + t_setup (plus skew).

A multiplexer with 2^k data inputs needs k select lines; an n-to-2^n decoder with enable can implement arbitrary functions using minterms.

A ripple-carry adder chains full adders; carry-lookahead adders compute generate (G = A·B) and propagate (P = A ⊕ B) to reduce carry delay.

A register file is an array of registers with read ports and write ports; a shift register moves bits one position per clock.

Asynchronous inputs to sequential logic must be synchronized to avoid metastability.

Common ALU opcodes include ADD, SUB, AND, OR, XOR, NOT, shift left, shift right, and set-less-than (SLT).

SLT sets the destination to 1 if the first operand is less than the second (signed), otherwise 0; SLTU compares unsigned.

Logical shifts fill with zeros; arithmetic right shift replicates the sign bit to preserve signed magnitude.

Shift amount is often taken from an immediate field or a register; variable shifts use a barrel shifter or shifter tree.

The ALU zero flag often drives conditional branch decisions (e.g., branch-if-equal when Z = 1).

Immediate operands are typically sign-extended before entering the ALU; the ALU result feeds the register write-back path.

A load/store address is computed by an ALU add of a base register and a sign-extended offset.

Instructions that affect flags (add/sub) write to the status register; logical operations usually clear carry and overflow.

A single-cycle datapath performs each instruction in one clock period; the clock period must cover the longest instruction path.

A multicycle datapath splits instructions into steps, using intermediate registers (IR, A, B, ALUOut) to hold values between cycles.

The program counter (PC) holds the address of the next instruction; PC+4 is computed by a dedicated adder in the datapath.

The register file has two read ports and one write port; write occurs on the clock edge when RegWrite is asserted.

Control signals (RegWrite, MemRead, MemWrite, ALUSrc, PCSrc, MemtoReg, RegDst) select datapath element behavior per instruction.

Hardwired control uses combinational logic derived from the opcode; microprogrammed control uses a control store of microinstructions.

A pipelined datapath overlaps instruction stages; hazards include structural, data (RAW), and control hazards.

Data forwarding (bypassing) resolves many RAW hazards; stalls (bubbles) are inserted when forwarding is insufficient.