ALU 101 flashcards

32 cards. Read the term and the definition here. The deck at the top of this page is optional.

ALU definition

A combinational circuit that performs arithmetic and bitwise logic operations on one or more operands and produces a result along with status flags such as zero, carry, overflow, and sign.

Zero flag

A status bit set to 1 when the ALU result is all zeros, and 0 otherwise. Often used to trigger branch-if-equal decisions.

Signed overflow condition

Overflow occurs when adding two operands of the same sign yields a result of the opposite sign, equivalently V = C_in(MSB) XOR C_out(MSB).

Two's complement subtraction

Computing A minus B by adding A to the bitwise complement of B plus one: A + (~B) + 1. The carry-out then acts as an active-low borrow.

Operation select lines

Control inputs to the ALU that choose which function (add, subtract, AND, OR, XOR, shift) is applied. k lines select among up to 2^k operations.

One-bit ALU cell

A building block containing a full adder plus a multiplexer that selects among sum, AND, OR, or XOR outputs based on the operation select lines.

Two's complement range

An n-bit two's complement integer spans from negative 2^(n-1) to 2^(n-1) minus 1. For 8 bits that is -128 through 127.

Sign extension

Widening a signed value by replicating its most significant bit into the new high-order positions, preserving the value's sign and magnitude.

IEEE 754 single precision

A 32-bit floating-point format with 1 sign bit, 8 exponent bits biased by 127, and 23 fraction bits; normalized value is 1.F times 2^(E-127).

Unsigned n-bit range

An n-bit unsigned integer represents values from 0 to 2^n minus 1. For 8 bits that is 0 through 255.

Hexadecimal grouping

Each hexadecimal digit corresponds to exactly 4 binary bits, so binary-to-hex conversion groups bits in fours starting from the radix point.

Two's complement negation

Negating a two's complement number requires inverting all bits and adding one. Zero has a single representation; the most negative value has no positive counterpart.

De Morgan's laws

The complement of a sum equals the product of the complements, and the complement of a product equals the sum of the complements: (A+B)' = A'B' and (AB)' = A'+B'.

NAND functional completeness

Any Boolean function can be implemented using only NAND gates, because NAND can synthesize NOT, AND, and OR operations.

XOR identity

A XOR B equals A'B plus AB'. Useful identities include A XOR 0 = A, A XOR 1 = A', and A XOR A = 0.

Absorption law

A Boolean identity stating that A + AB = A and A(A + B) = A, allowing redundant terms to be eliminated during simplification.

Minterm definition

A product term that is true for exactly one combination of input variables. Summing minterms produces a canonical sum-of-products expression.

Combinational versus sequential

Combinational logic outputs depend only on current inputs, while sequential logic outputs depend on current inputs and previously stored state.

D flip-flop behavior

A clocked storage element that captures and holds the value on input D at the active clock edge, unlike a level-sensitive latch.

Setup and hold time

Setup time is how long data must be stable before a clock edge; hold time is how long it must remain stable after the edge.

Carry-lookahead adder

An adder that computes generate (G = A AND B) and propagate (P = A XOR B) signals to determine carries in parallel, reducing carry propagation delay.

Multiplexer select lines

A multiplexer with 2^k data inputs requires k select lines to choose which input is routed to the single output.

Metastability

An unstable state a flip-flop may enter when its input changes near the clock edge; asynchronous inputs are synchronized to avoid it.

Set-less-than operation

An ALU operation producing 1 when the first operand is less than the second and 0 otherwise; the unsigned variant compares magnitudes without sign.

Arithmetic right shift

A right shift that replicates the sign bit into vacated high-order positions, preserving the sign of a two's complement value.

Logical shift

A shift operation that fills vacated bit positions with zeros, used for unsigned magnitude manipulation rather than signed division.

Immediate sign extension

Before entering the ALU, an immediate operand is typically sign-extended to full width so signed arithmetic and address offsets remain correct.

Load/store address computation

A memory address is formed by adding a base register value to a sign-extended offset using the ALU adder.

Single-cycle datapath

A processor organization where every instruction completes in one clock period; the period must accommodate the longest instruction path.

Program counter

A register holding the address of the next instruction to fetch. In many designs PC+4 is computed by a dedicated adder in the datapath.

Control signals

Signals such as RegWrite, MemRead, MemWrite, ALUSrc, and PCSrc that configure datapath elements for each instruction's required behavior.

Data forwarding

A pipelining technique that routes a result directly from a later stage back to an earlier stage to resolve read-after-write data hazards without stalling.