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ALU 101: Combinational and Sequential Logic

ALU 101 · Work through your exam, one topic at a time.

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Combinational and Sequential Logic

Two families of circuits

Combinational logic has no memory: outputs depend only on current inputs (adders, multiplexers, decoders, comparators). Sequential logic stores state: outputs depend on inputs and prior state, clocked by a clock signal (flip-flops, registers, counters). Candidates must distinguish them and know that feedback is what creates memory.

Building blocks

Know the behavior of multiplexers (select one of many inputs), decoders (one-hot output for each input code), encoders, and adders (half adder: sum = A XOR B, carry = A AND B; full adder adds carry-in). For sequential logic, know SR, D, JK, and T flip-flops, edge-triggering versus level-triggering, and setup/hold timing constraints. Understand race conditions and hazards in combinational networks.

Traps to watch

  • Calling a latch edge-triggered - latches are level-sensitive; flip-flops are edge-triggered.
  • Forgetting that a D flip-flop simply passes input to output on the clock edge (Q_next = D).
  • Ignoring setup and hold times, which cause metastability if violated.
  • Assuming a ripple counter changes all bits simultaneously - it does not; skew accumulates.
  • Confusing a decoder (n inputs to 2^n outputs) with a multiplexer (2^n inputs to 1 output).

Rule of thumb

Ask: "Can the output change without a new input event?" If yes, the circuit has state and is sequential. If the output is a pure function of present inputs, it is combinational.

Worked example: A full adder has inputs A, B, Cin. Sum = A XOR B XOR Cin; Cout = (A AND B) OR (Cin AND (A XOR B)). For A=1, B=1, Cin=1: Sum = 1 XOR 1 XOR 1 = 1, Cout = 1. That is 3 in binary (11). Correct.