Datapath, Registers, and Control
Structure of the datapath
The datapath is the network of registers, the ALU, multiplexers, and buses that move and transform data. Candidates should be able to describe a simple processor datapath: program counter, instruction register, register file, ALU, and memory interface. Understand the register file as a small fast array with read ports and a write port, and the role of multiplexers in selecting ALU inputs and write-back sources.
Control
Control generates the select and enable signals that steer the datapath each cycle. Know the difference between hardwired control (combinational logic decoding the opcode) and microprogrammed control (a control store of microinstructions). Understand the fetch-decode-execute cycle, single-cycle versus multi-cycle versus pipelined timing, and that the clock period must accommodate the longest path.
Traps to watch
- Confusing the control unit (generates signals) with the datapath (moves and transforms data).
- Assuming all registers can be written simultaneously - usually one write port per cycle.
- Forgetting that the program counter must update every cycle, including during branches.
- Mixing up single-cycle (CPI = 1, long clock) with pipelined (higher throughput, hazards possible).
- Overlooking that register writes are typically edge-triggered while reads are combinational.
Rule of thumb
Separate "what moves" (datapath) from "who decides" (control). For any cycle, list the control signals asserted and the resulting register transfers.
Worked example: ADD R1, R2, R3: control asserts register-file read for R2 and R3, selects ALU add, and asserts write-enable for R1. Next edge, R1 receives the sum. The PC increments in parallel. Naming these signals is the answer to "describe the datapath activity."