The Thevenin model that does not survive a load resistor
A student characterises an unfamiliar sensor module at its output terminals. With a 10 MΩ DMM the open-circuit output reads 4.00 V. Shorting the output through a 10 Ω shunt ammeter gives 2.00 mA. Loading the output with a 1.00 kΩ resistor makes the terminal voltage fall to 1.60 V. All three readings were taken on the same 5 V supply, and the module datasheet states a maximum output drive current of 3 mA but says nothing about output impedance. The student intends to build a Thevenin model from the open-circuit and short-circuit readings and then connect the sensor directly to a 12-bit ADC (4.096 V full scale, 200 kSa/s, 2 µs acquisition window) through 10 m of shielded cable with 100 pF/m. A colleague argues the model is fine because the meter is 10 MΩ and therefore does not load the circuit at all.
1. The open-circuit/short-circuit route implies Rth = 2.0 kΩ; the 1 kΩ load implies something else. Work out both numbers, decide which model to trust, and justify the decision physically rather than statistically.
Read the worked answer
From the loaded point. The 1.00 kΩ load carries 1.60 V / 1.00 kΩ = 1.60 mA. The drop across the internal resistance is 4.00 − 1.60 = 2.40 V, so
Rth = 2.40 V / 1.60 mA = 1.50 kΩ.
From Voc/Isc. 4.00 V / 2.00 mA = 2.00 kΩ.
Cross-check. If Rth were 2.0 kΩ, the 1.0 kΩ load would give 4.00 × 1.0/3.0 = 1.33 V, not the measured 1.60 V. The two models cannot both be right.
Which is wrong and why. The 2.0 kΩ figure assumes two things that are not true here:
- Linearity. Voc/Isc is only a valid two-point estimate if the source is a fixed voltage behind a fixed resistance. The datasheet's 3 mA output-drive limit is the giveaway: the measured short-circuit current of 2.00 mA sits at the knee of a current limit, so the output stage is no longer a linear Thevenin source at that operating point.
- A true short. The ammeter inserts 10 Ω, which is only 0.5% of 2 kΩ and therefore cannot explain the discrepancy; do not blame the meter when the burden is negligible and a drive limit is specified.
The 1.5 kΩ model is the one to keep, with the caveat that it is valid only while the load current stays well below 3 mA. The correct diagnostic step is a third load point (say 4.7 kΩ), which should fall on the line through (4.00 V, 0 mA) and (1.60 V, 1.60 mA).
2. Using the model you trust, find the load for maximum power transfer and check whether that operating point is actually usable. Then state whether the direct cable-to-ADC connection will meet 1 LSB accuracy.
Read the worked answer
Maximum power transfer.
P_max = Voc² / (4·Rth) = (4.00)² / (4 × 1500) = 2.67 mW, at RL = Rth = 1.50 kΩ.
At that point the terminal voltage is 2.00 V, the current is 2.00/1500 = 1.33 mA, and the voltage drop across Rth is 2.00 V. The current of 1.33 mA is inside the 3 mA drive limit, so the calculation is self-consistent - unlike the short-circuit measurement.
Direct connection to the ADC.
- Cable capacitance: 10 m × 100 pF/m = 1 nF. The ADC's 10 pF is negligible beside it.
- Settling time constant: τ = Rth × C = 1500 Ω × 1 nF = 1.5 µs.
- The acquisition window is 2 µs, i.e. only 2/1.5 ≈ 1.33τ, so the sample has settled to only 1 − e^(−1.33) ≈ 74% of the final value. That is a gross error, not an LSB-level one.
- To land within 1 LSB of a 4.096 V, 12-bit converter (1 mV, i.e. 1 part in 4096), you need about 9.3τ: t_acq/9.3 = 215 ns, so the total allowable source-plus-cable capacitance at 1.5 kΩ is roughly 143 pF. The cable alone is seven times that.
Conclusion. The Thevenin model is fine, but the load it is asked to drive is not. Add a unity-gain buffer at the sensor terminals (or move the ADC next to the sensor), and keep the cable on the low-impedance side of the buffer. A 1.5 kΩ source driving 1 nF through a connector is also a 106 kHz pole, which will not matter at DC but will ruin any multiplexed scan.
3. The same module is later used with a 30 cm ribbon cable and shows crosstalk into an adjacent 1 kHz digital line. Explain the mechanism in terms of the model you derived, and state the two cheapest mitigations ranked by effectiveness.
Read the worked answer
Mechanism. The source impedance is 1.5 kΩ, and the signal line is a high-impedance, capacitively coupled node:
- Coupling capacitance between adjacent ribbon conductors (typically 30–100 pF/m for 0.05-inch ribbon) forms a capacitive divider with the cable-to-ground capacitance and the load capacitance.
- The divider ratio is roughly C_couple / (C_couple + C_node). With ~20 pF of coupling and ~1 nF of node capacitance, the coupled step is small per edge - but the victim node's recovery is governed by τ = Rth·C = 1.5 µs, so each aggressor edge injects a charge packet that takes microseconds to decay while the aggressor returns every 1 ms. The result is a series of small pedestals that a 12-bit converter easily resolves, especially if sampling is not synchronised to the aggressor.
Mitigations, best first:
- Buffer at the source. Dropping the driving impedance from 1.5 kΩ to tens of ohms reduces both the divider recovery time and the susceptibility by roughly two orders of magnitude. This is the fix that also solves the ADC settling problem, so it is effectively free.
- Interleave grounds. Replace the ribbon with a flat cable having a ground return between every signal, or use twisted pairs. This cuts C_couple by an order of magnitude and closes the loop area.
Adding a capacitor to ground at the receiver is the tempting third option, but it lowers the divider ratio only by increasing C_node while lengthening τ further; it trades amplitude for settling time and is usually a net loss at 12 bits.