ESECE cheat sheet

Nodal analysis: write KCL at each non-reference node; a current leaving the node is positive. Unknowns = independent nodes; solve the conductance matrix G·V = I where G is symmetric for reciprocal networks.

Mesh analysis: write KVL around each independent mesh; a shared branch carries the difference of the two mesh currents. Use mesh currents only for planar networks; non-planar networks need loop or nodal analysis.

Superposition applies only to linear circuits: set each independent voltage source to 0 V (short) and each independent current source to 0 A (open), sum the individual responses. It fails for power and for any nonlinear element.

Thevenin equivalent: V_th = open-circuit voltage at the port, R_th = V_oc / I_sc, or set all independent sources to zero and look in. The load receives maximum power when R_L = R_th, giving P_max = V_th² / (4 R_th).

Norton transform: I_N = V_th / R_th and R_N = R_th, so a Thevenin source in series with R converts to a Norton current source in parallel with the same R.

First-order step response: x(t) = x(∞) + [x(0⁺) − x(∞)]·e^(−t/τ), with τ = R_th·C for RC and τ = L / R_th for RL. Capacitor voltage and inductor current are continuous; resistor current and capacitor current can jump.

Second-order series RLC: characteristic roots s = −α ± √(α² − ω₀²), with α = R/(2L) and ω₀ = 1/√(LC). Overdamped if α > ω₀, critically damped if α = ω₀, underdamped if α < ω₀.

Resonance: at ω₀ = 1/√(LC) the series circuit impedance is purely resistive and minimum; the quality factor is Q = ω₀L/R = (1/R)√(L/C). Bandwidth Δω = ω₀/Q.

Star-delta (Y-Δ) conversion: R_A = (R_AB·R_AC)/(R_AB + R_BC + R_CA), and the inverse R_AB = (R_A R_B + R_B R_C + R_C R_A)/R_C. Use it to collapse bridge networks that are neither series nor parallel.

BJT regions: cutoff when V_BE < 0.7 V, active when the base-emitter junction is forward biased and the base-collector junction is reverse biased (I_C = βI_B), saturation when both junctions are forward biased (V_CE ≈ 0.2 V).

Small-signal BJT parameters: g_m = I_C / V_T with V_T ≈ 26 mV at room temperature, r_π = β/g_m, and r_e = V_T / I_E. Voltage gain of a common-emitter stage with bypassed emitter: A_v ≈ −g_m·(R_C ∥ R_L).

MOSFET saturation condition: V_DS > V_GS − V_th. Then I_D = ½·k_n′·(W/L)·(V_GS − V_th)²·(1 + λV_DS). In triode, I_D = k_n′·(W/L)·[(V_GS − V_th)V_DS − V_DS²/2].

Op-amp ideal assumptions: infinite open-loop gain, infinite input impedance, zero output impedance, infinite bandwidth. With negative feedback, the summing-point constraint forces V₊ = V₋ and zero input current.

Op-amp configurations: inverting gain = −R_f/R_in; non-inverting gain = 1 + R_f/R_g; voltage follower gain = 1; integrator output = −(1/RC)∫v_in dt; differentiator output = −RC·dv_in/dt.

Ideal op-amp circuits: a difference amplifier gives V_out = (R_f/R_in)(V₂ − V₁) only when both resistor ratios match. Slew rate limits large-signal frequency: the full-power bandwidth is f_max = SR / (2π·V_peak).

Feedback: negative feedback increases bandwidth and input impedance (for series-voltage feedback) and reduces gain by the factor (1 + Aβ). The circuit oscillates when the loop gain Aβ = 1 with 180° of additional phase shift (Barkhausen criterion).

Bias stability: an emitter resistor R_E with a bypass capacitor stabilizes the operating point against β variation; the bias is β-independent when βR_E ≫ R_B. Thermal runaway is avoided by keeping V_CE moderate.

Class of operation: Class A conducts 360° (max efficiency 25% resistive load, 50% transformer-coupled), Class B conducts 180° (78.5% max), Class AB reduces crossover distortion, Class C conducts less than 180° and is used for RF power.

Boolean identities: A + A′B = A + B, A + AB = A, A·A′ = 0, A + A′ = 1. De Morgan: (A·B)′ = A′ + B′ and (A + B)′ = A′·B′.

Canonical forms: any function can be written as a sum of minterms (SOP) or a product of maxterms (POS). A Karnaugh map groups 1s in powers of two, and wrap-around grouping across edges is allowed.

Combinational building blocks: a 2-to-1 mux implements F = S′I₀ + SI₁; an n-to-2ⁿ decoder with an OR gate realizes any n-variable function; a full adder has Sum = A ⊕ B ⊕ C_in and C_out = AB + C_in(A ⊕ B).

Flip-flop behavior: D captures Q = D on the clock edge; JK toggles when J = K = 1; T toggles when T = 1. Setup and hold times must be met at every edge-triggered input.

Counters: an n-bit ripple counter divides the clock by 2ⁿ; a modulo-N counter needs ⌈log₂N⌉ flip-flops. Synchronous counters clock all flip-flops in parallel, avoiding ripple delay accumulation.

State machines: a Mealy machine's output depends on state and input (fewer states, output can glitch); a Moore machine's output depends only on state (registered output, one cycle later).

Number systems: two's complement negation is invert-all-bits-plus-one; an n-bit two's complement range is −2^(n−1) to 2^(n−1) − 1. BCD uses 4 bits per decimal digit and codes 1010–1111 are invalid.

Static hazards appear when two paths with different delays reconverge; add a redundant consensus term (e.g., AB + A′C + BC) to remove the glitch.

CMOS logic: a pull-up network of PMOS transistors and a pull-down network of NMOS form a complementary pair; static CMOS draws essentially no DC current, and dynamic power is P = α·C·V_DD²·f.

Linearity requires both additivity and homogeneity; time invariance requires x(t − t₀) → y(t − t₀). A system is causal if the output at t depends only on inputs at times ≤ t.

Convolution: y(t) = ∫x(τ)h(t − τ)dτ, and in discrete time y[n] = Σx[k]h[n − k]. A system is BIBO stable if and only if ∫|h(t)|dt < ∞ (or Σ|h[n]| < ∞).

Fourier transform pairs: rect(t/T) ↔ T·sinc(fT); e^(−at)u(t) ↔ 1/(a + jω); δ(t) ↔ 1; cos(ω₀t) ↔ π[δ(ω − ω₀) + δ(ω + ω₀)]. Multiplication in time is convolution in frequency.

Parseval's theorem: total energy equals the integral of |X(f)|² over all frequencies. For a periodic signal, power is the sum of squared Fourier-series coefficient magnitudes.

Sampling theorem: a bandlimited signal with maximum frequency f_max is reconstructible if f_s > 2f_max. Aliased frequencies fold to f_s − f. An anti-aliasing low-pass filter precedes the ADC.

Laplace transform: L{e^(−at)u(t)} = 1/(s + a). A causal LTI system is stable if and only if all poles lie in the open left half-plane; the ROC must include the jω axis.

z-transform: x[n] = aⁿu[n] ↔ z/(z − a) for |z| > |a|. A discrete LTI system is stable if and only if all poles lie strictly inside the unit circle.

LTI eigenfunction property: a complex exponential e^(jωt) passes through with gain H(jω). A real system has conjugate-symmetric frequency response, so |H(jω)| is even and ∠H(jω) is odd.

Group delay is −dφ/dω; a linear-phase filter has constant group delay. Ideal filters (rectangular magnitude) are non-causal and unrealizable, requiring approximation such as Butterworth or Chebyshev responses.

Maxwell's equations in point form: ∇·D = ρ_v, ∇·B = 0, ∇×E = −∂B/∂t, ∇×H = J + ∂D/∂t. In a source-free linear medium, waves travel at v = 1/√(με).

Intrinsic impedance of free space η₀ = √(μ₀/ε₀) ≈ 377 Ω; in a general medium η = √(μ/ε). The propagation constant is γ = α + jβ = √(jωμ(σ + jωε)).

Transmission-line primary parameters: R, L, G, C per unit length. The characteristic impedance is Z₀ = √((R + jωL)/(G + jωC)); for a lossless line Z₀ = √(L/C) and v_p = 1/√(LC).

Reflection coefficient Γ = (Z_L − Z₀)/(Z_L + Z₀), with VSWR = (1 + |Γ|)/(1 − |Γ|). Γ = 0 and VSWR = 1 when the load equals Z₀ (matched).

A shorted line (Z_L = 0) gives Γ = −1; an open line (Z_L = ∞) gives Γ = +1. A quarter-wave line (length λ/4) transforms Z_L to Z₀²/Z_L, acting as an impedance inverter.

Input impedance: Z_in = Z₀·(Z_L + jZ₀ tan βl)/(Z₀ + jZ_L tan βl), with β = 2π/λ. A line shorter than λ/4 with a capacitive load looks inductive and vice versa.

Smith chart: a full rotation is λ/2, and moving toward the generator is clockwise. Normalized resistance and reactance circles are orthogonal; the center represents a matched load.

Poynting vector S = E × H gives power density in W/m². Average power density of a uniform plane wave is |E|²/(2η).

Boundary conditions: tangential E is continuous, and tangential H jumps by the surface current density. At a perfect conductor, tangential E = 0 and normal B = 0.

Intrinsic carrier concentration: n_i² = N_C·N_V·e^(−E_g/kT). At 300 K, silicon has n_i ≈ 1.5×10¹⁰ cm⁻³ and E_g ≈ 1.12 eV. Mass-action law: n·p = n_i².

Doped material: n-type has N_D donors and n ≈ N_D, p ≈ n_i²/N_D; p-type has N_A acceptors and p ≈ N_A. Fermi level shifts toward the conduction band for n-type and the valence band for p-type.

Diode equation: I = I_S·(e^(V/(nV_T)) − 1), with V_T ≈ 26 mV at 300 K. Forward drop is ≈ 0.7 V for silicon and ≈ 0.3 V for germanium or Schottky devices.

Depletion width of a one-sided p⁺n junction: W ≈ √(2εV_bi/(qN_D)), so W scales as 1/√N_D. Junction capacitance C_j ∝ 1/√(V_bi − V) and acts as a varactor when reverse biased.

BJT current gain: α = I_C/I_E, β = I_C/I_B, and β = α/(1 − α). The base is thin and lightly doped so that emitter injection efficiency and base transport factor stay near unity.

MOSFET threshold voltage includes flat-band voltage, depletion charge, and oxide capacitance: V_th = V_FB + 2φ_F + √(2ε_s qN_A·2φ_F)/C_ox. Below threshold, current is exponential (subthreshold).

MOSFET channel-length modulation makes the output resistance finite: r_o ≈ 1/(λI_D). Velocity saturation in short-channel devices makes I_D roughly linear rather than quadratic in overdrive.

Breakdown mechanisms: avalanche multiplication dominates above ≈ 6 V (positive temperature coefficient); Zener tunneling dominates below ≈ 5 V (negative temperature coefficient).

Hall effect: V_H = I·B/(q·n·t). The sign of V_H identifies carrier type, and the magnitude gives carrier concentration; mobility follows from conductivity σ = qnμ.

AM-DSB-FC: s(t) = A_c[1 + m(t)]cos(2πf_c t); modulation index μ = A_m/A_c. Bandwidth is 2f_m, and the total power is P_c(1 + μ²/2). Overmodulation (μ > 1) causes envelope distortion.

DSB-SC and SSB: DSB-SC bandwidth is 2f_m and requires coherent detection; SSB bandwidth is f_m and saves half the bandwidth and power but needs a sharp sideband filter or phasing network.

FM: Carson's rule gives bandwidth B ≈ 2(Δf + f_m), with deviation ratio β = Δf/f_m. FM has constant envelope (immune to amplitude noise) but consumes more bandwidth than AM.

Noise: thermal noise power in bandwidth B is N = kTB, with k = 1.38×10⁻²³ J/K. Noise figure F = SNR_in/SNR_out, and for cascaded stages Friis gives F_total = F₁ + (F₂ − 1)/G₁ + …

PCM: the signal-to-quantization-noise ratio for a full-scale sinusoid is SNR ≈ 6.02n + 1.76 dB for n bits. The minimum sampling rate is 2f_m (Nyquist), and bit rate is R_b = n·f_s.

Digital modulation: BPSK and QPSK have the same BER expression Q(√(2E_b/N₀)) but QPSK doubles spectral efficiency. M-QAM requires roughly 3 dB more E_b/N₀ per doubling of M for the same BER.

Shannon capacity: C = B·log₂(1 + S/N) bit/s. It sets the upper bound regardless of coding; the Shannon limit is E_b/N₀ ≈ −1.6 dB for infinite bandwidth.

Matched filter maximizes output SNR at the sampling instant; its impulse response is a time-reversed copy of the pulse, and the maximum SNR is 2E/N₀.

Error control: Hamming distance d_min allows detection of d_min − 1 errors and correction of ⌊(d_min − 1)/2⌋ errors. A (7,4) Hamming code has d_min = 3 and corrects one error.

Transfer function: G(s) = C(s)/R(s) for zero initial conditions. Poles are roots of the denominator; the system is stable if all poles have negative real parts (continuous time).

First-order step response: y(t) = K(1 − e^(−t/τ)); rise time (10–90%) ≈ 2.2τ, settling time (2%) ≈ 4τ. Second-order: ω_n and ζ, with percent overshoot = 100·e^(−ζπ/√(1−ζ²)).

Second-order specifications: peak time t_p = π/(ω_n√(1 − ζ²)), settling time (2%) ≈ 4/(ζω_n). Underdamped if 0 < ζ < 1, critically damped if ζ = 1, overdamped if ζ > 1.

Routh-Hurwitz: build the array from the characteristic polynomial coefficients; the number of sign changes in the first column equals the number of right-half-plane poles. A zero row is resolved with the auxiliary polynomial.

Steady-state error depends on system type: with a step input, e_ss = 1/(1 + K_p); with a ramp, e_ss = 1/K_v; with a parabola, e_ss = 1/K_a. Type 0 has finite step error and infinite ramp error.

Bode plots: a pole at the origin gives −20 dB/decade slope and −90° phase; each additional pole adds −20 dB/decade and −90°. The gain crossover frequency is where |G| = 1 (0 dB).

Stability margins: gain margin is the negative of the gain at the phase crossover (−180°); phase margin is 180° plus the phase at the gain crossover. Typical design targets are PM ≥ 45° and GM ≥ 6 dB.

Root locus rules: branches start at open-loop poles and end at open-loop zeros; the locus lies on the real axis to the left of an odd number of poles plus zeros; the centroid is σ_a = (Σp − Σz)/(n − m).

PID control: proportional action reduces rise time; integral action eliminates steady-state error but reduces stability; derivative action adds damping and amplifies high-frequency noise, so it is filtered in practice.

8051 architecture: 8-bit CPU, 4 KB internal ROM, 128 bytes RAM, two 16-bit timers, five interrupt sources, and four 8-bit ports. Register banks occupy 00H–1FH of internal RAM.

8051 memory: program memory is accessed with MOVC (code) and data memory with MOVX (external). The PSW carries the carry, auxiliary carry, overflow, and register-bank-select bits.

ARM Cortex-M: 32-bit RISC with Thumb-2 instructions, a nested vectored interrupt controller, and separate stack pointers for handler and thread modes. The vector table starts at address 0x00000000 (relocatable via VTOR).

Memory-mapped I/O: peripherals are accessed through fixed addresses, so a store to a peripheral register drives hardware. Bit-banding on Cortex-M maps a bit to a 32-bit alias word for atomic bit access.

Interrupts: an interrupt pushes the return address and status onto the stack, then jumps to the vector. Latency is reduced by tail-chaining and late-arriving preemption in the NVIC.

Serial buses: I²C uses two wires (SDA, SCL) with 7-bit addressing and open-drain pull-ups; SPI uses four wires (MOSI, MISO, SCK, CS) and is full duplex; UART is asynchronous with a start and stop bit.

ADC resolution: an n-bit ADC maps full scale to 2ⁿ codes, so the step is V_ref/2ⁿ. Successive approximation takes n comparisons, one per bit, and is common in embedded MCUs.

Timers and PWM: a compare register sets the duty cycle and the period register sets the frequency; f_PWM = f_clock/(prescaler·(period + 1)).

Endianness and alignment: little-endian stores the least significant byte at the lowest address. Unaligned multi-byte access can fault on some architectures, so packed structs must be handled carefully.

Per-unit: Z_pu = Z_actual/Z_base with Z_base = V_base²/S_base. Per-unit impedance is the same on either side of a transformer when the bases follow the turns ratio.

Three-phase power: S = √3·V_L·I_L, P = √3·V_L·I_L·cos φ, and Q = √3·V_L·I_L·sin φ. For a balanced Y load, phase voltage is line voltage divided by √3.

Transformer: EMF equation E = 4.44·f·N·Φ_max. Equivalent impedance is found from the short-circuit test, and core loss from the open-circuit test. Efficiency peaks when copper loss equals core loss.

Induction motor: synchronous speed n_s = 120f/P; slip s = (n_s − n)/n_s; rotor frequency is sf. Starting torque is zero at s = 0 and maximum at s = R₂/X₂.

Synchronous machine: E = V + I_a(R_a + jX_s) per phase. The machine is overexcited (leading) when E > V and supplies reactive power; the power-angle equation is P = (EV/X_s)·sin δ.

DC machines: E_b = (P·Φ·N·Z)/(60A) and torque T = (P·Φ·I_a·Z)/(2πA). For a shunt motor, speed falls slightly with load; for a series motor, torque is roughly proportional to I_a².

Transmission: real power flow is P ≈ (V₁V₂/X)·sin δ, and reactive flow is dominated by the voltage magnitude difference. A series capacitor reduces X and raises the power limit.

Faults: a three-phase fault is symmetrical and is analyzed with a single positive-sequence network. Unsymmetrical faults use symmetrical components (positive, negative, zero sequence).

Protection: a CT steps current down and a PT steps voltage down. Overcurrent relays have inverse-time characteristics; distance relays reach a set fraction (typically 80%) of the line impedance.