ESECE key terms

A two-terminal linear network replaced by a single voltage source in series with one resistance; the source is the open-circuit voltage and the resistance is that seen with all independent sources zeroed.

A two-terminal linear network replaced by a current source in parallel with a resistance; the current is the short-circuit current and the resistance equals the Thevenin resistance of the same network.

In a linear circuit with several independent sources, the total response equals the algebraic sum of responses computed with each source acting alone while the others are deactivated: voltage sources shorted, current sources opened.

The frequency at which a series or parallel RLC circuit's inductive and capacitive reactances cancel, giving unity power factor and, for series resonance, minimum impedance and maximum current.

A dimensionless measure of resonator selectivity, equal to the ratio of stored energy to energy lost per radian; for a series RLC it is (1/R) times the square root of L/C.

The cosine of the angle between voltage and current phasors at a port; it equals real power divided by apparent power and indicates how effectively current delivers useful power.

A linear approximation of a nonlinear device around a DC operating point, replacing it with incremental resistances and controlled sources such as transconductance, valid only for small excursions about that bias point.

The ratio of a small change in output current to the small change in input voltage that causes it, denoted gm; it sets the voltage gain of a field-effect or bipolar transistor stage.

The DC voltage and current at a transistor's terminals with no signal applied; bias networks establish it so the device stays in its intended region and signal swings remain undistorted.

The maximum rate of change of an operational amplifier's output voltage, usually quoted in volts per microsecond; it limits large-signal high-frequency response and causes triangular distortion when exceeded.

For an op-amp with a single dominant pole, the constant product of closed-loop gain and the frequency at which that gain falls by 3 dB; it marks the unity-gain crossover frequency.

A rectangular grid arranging truth-table minterms so adjacent cells differ in one variable, allowing visual grouping of cells into minimal sum-of-products expressions for combinational logic.

An input combination whose output is unspecified because it never occurs or its value is irrelevant; such minterms may be grouped either way to simplify logic.

The minimum interval a synchronous input must remain stable before the active clock edge for the flip-flop to capture it reliably; violating it risks metastability.

The minimum interval a synchronous input must stay stable after the active clock edge so the flip-flop latches the correct value; it is distinct from, and usually shorter than, setup time.

A condition in which a bistable element's output hovers between valid logic levels for an unpredictable time after a timing violation, resolving randomly and potentially causing system failure.

The minimum sampling frequency, twice the highest frequency present in a bandlimited signal, at which the signal can be reconstructed exactly from its samples without aliasing.

The folding of high-frequency content onto lower frequencies when a signal is sampled below its Nyquist rate, producing irreversible distortion unless an anti-alias filter precedes the sampler.

The discrete-time counterpart of the Laplace transform, mapping a sequence to a function of complex variable z; its region of convergence determines stability and causality of an LTI system.

The ratio of voltage to current for a single wave travelling on a uniform transmission line, set by line inductance and capacitance per unit length; typically 50 or 75 ohms.

The complex ratio of reflected to incident wave amplitude at a discontinuity, equal to load impedance minus characteristic impedance over their sum; zero means a matched load.

The ratio of maximum to minimum voltage magnitude along a line carrying incident and reflected waves; it equals one for a matched load and grows with mismatch.

The distance into a conductor at which current density falls to 1/e of its surface value; it shrinks as the square root of frequency, raising effective resistance at high frequency.

The zone near a p-n junction depleted of mobile carriers by diffusion of electrons and holes, leaving fixed ionized dopants that create a built-in potential and junction capacitance.

The equilibrium voltage across a p-n junction's depletion region, roughly 0.7 V for silicon, arising from the balance between diffusion and drift of carriers.

Reverse breakdown in a heavily doped junction where a strong field lets electrons tunnel across the depletion region; the voltage is nearly constant and used for regulation.

For a field-effect transistor, the change in drain current divided by the change in gate-source voltage; it rises with bias current and governs amplifier gain.

The maximum error-free data rate over a noisy channel, C = B log2(1 + S/N), where B is bandwidth and S/N is the linear signal-to-noise power ratio.

The ratio of signal power to noise power at a point in a system, usually expressed in decibels; it bounds achievable fidelity and error rate.

The range of frequencies a system passes or occupies, commonly measured between half-power points; it trades against noise and sets the maximum symbol rate.

A pair of graphs showing a system's magnitude in decibels and phase in degrees versus logarithmic frequency, used to read gain margin and phase margin from the open-loop response.

The amount by which open-loop phase exceeds minus 180 degrees at the frequency where open-loop gain is unity; it indicates relative stability of the closed-loop system.

The factor by which loop gain can increase before the closed-loop system becomes unstable, measured at the frequency where open-loop phase reaches minus 180 degrees.

A stored address or index that tells the processor where to jump when a particular interrupt is asserted, allowing each source to have its own service routine.

An addressing scheme in which peripheral registers occupy the same address space as memory, so ordinary load and store instructions access devices without special I/O opcodes.

The fraction of each switching period during which a pulse-width-modulated signal is high; in a buck converter it approximately equals output voltage divided by input voltage.

The fractional difference between synchronous speed and actual rotor speed of an induction machine, positive in motoring and negative in generation; it determines rotor frequency and torque.

A normalization in which voltages, currents, and impedances are divided by chosen base values, simplifying transformer banks and power-flow calculations by removing turns-ratio scaling.