Phase margin, transport delay and the temptation to just lower the gain
A single-axis position servo uses a digital PI controller sampling at 100 Hz, driving a current-mode servo drive that saturates at ±10 V. Open-loop identification of the plant, from 0.1 to 100 rad/s, matches G(s) = 10/(s(0.1s + 1)(0.05s + 1)) to within 1 dB and 5°. Commissioning runs with Kp = 1 V/rad, Ki = 0 and unity feedback; a 1 rad step gives about 35% overshoot with four visible oscillations before settling, and the commissioning log records a phase margin of 33°. The encoder interface and drive filter add a transport delay that the engineer estimates at 30 ms but has not measured. On large slews the position error stays at about 25% of full scale for 200 ms while the drive output sits at its 10 V limit; when the axis finally arrives, it overshoots far more than the small-signal test predicts. The specification is overshoot ≤ 10%, settling ≤ 0.5 s, and no degradation of overshoot after a saturated slew.
1. Compute the gain crossover frequency and phase margin by hand, include the 30 ms delay, and reconcile the result with the logged 33° and the observed 35% overshoot.
Read the worked answer
Gain crossover.
|G(jω)| = 10 / ( ω·√(1 + 0.01ω²)·√(1 + 0.0025ω²) )
At ω = 7.5 rad/s: 10 / (7.5 × 1.25 × 1.068) = 10/10.01 ≈ 1. So ω_c ≈ 7.5 rad/s.
Phase there:
∠G = −90° − atan(0.75) − atan(0.375) = −90° − 36.9° − 20.6° = −147.5°
⇒ phase margin = 180° − 147.5° = 32.5°.
That matches the logged 33° almost exactly, which confirms the identification and the Kp value.
Now add the delay. At 7.5 rad/s, 30 ms of transport delay contributes ω·T = 0.225 rad = 12.9° of extra lag. True phase margin = 32.5° − 12.9° ≈ 19.6°.
Reconciliation. The log's 33° is inconsistent with a 30 ms delay unless the delay is smaller than estimated (about 5 ms would explain 33°). The 35% overshoot corresponds to a damping ratio near 0.32, which is what you get from roughly 20–25° of margin, not 33°. The most likely explanation is that the delay was never in the loop when the margin was measured - the drive filter or encoder link was bypassed, or the measurement was taken on the command path. Action: measure the delay directly with a step and cross-correlation before designing any compensator; the whole design hinges on it.
2. The obvious remedy is to reduce Kp until the phase margin reaches 50°. Evaluate this quantitatively against the settling specification.
Read the worked answer
What gain alone buys. Find the frequency where the total phase (plant plus delay) is −130°, i.e. PM = 50°:
−90 − atan(0.1ω) − atan(0.05ω) − 0.03ω(rad) = −130
Try ω = 4 rad/s: −90 − 21.8 − 11.3 − 6.9 = −130.0°. Exactly on target.
Gain needed. |G(j4)| = 10 / (4 × 1.077 × 1.020) = 2.276, so
Kp = 1/2.276 ≈ 0.44.
Cost.
- Crossover falls from 7.5 to 4 rad/s - the closed-loop bandwidth drops by nearly half. With ζ ≈ 0.5 at PM 50°, settling time ≈ 4/(ζω_n) ≈ 4/(0.5 × 4) ≈ 2 s, four times the 0.5 s specification. Gain reduction cannot meet the settling requirement.
- DC loop gain falls by 2.3×. With Ki = 0 this shows up as a velocity-error constant reduced from 10 s⁻¹ to 4.4 s⁻¹, i.e. tracking lag on ramps more than doubles, and disturbance rejection degrades by the same factor.
Conclusion. Lowering Kp trades the specification you must keep (speed) for the one you can fix another way (damping). It is the right move only if the delay is much smaller than 30 ms and the settling spec is soft - neither is true here.
3. Propose a compensator that meets PM ≥ 50° with crossover near the original bandwidth, and add the anti-windup scheme needed for the saturated slew. Give numbers.
Read the worked answer
Lead compensator. Place a zero at 5 rad/s and a pole at 25 rad/s:
C(s) = (1 + s/5)/(1 + s/25), with unit DC gain.
At ω = 8 rad/s the lead contributes atan(1.6) − atan(0.32) = 58.0° − 17.7° = +40.3°.
Check the loop at 8 rad/s:
- Plant phase: −90 − atan(0.8) − atan(0.4) = −90 − 38.7 − 21.8 = −150.5°
- Delay: 8 × 0.03 = 0.24 rad = 13.8° → −164.3°
- With lead: −164.3 + 40.3 = −124.0° ⇒ PM = 56° ✓
Gain: |G(j8)| = 10/(8 × 1.281 × 1.077) = 0.907; lead magnitude = √(1+2.56)/√(1+0.102) = 1.797. Product = 1.63, so set K = 1/1.63 ≈ 0.61.
Crossover stays at 8 rad/s (near the original 7.5), so settling is preserved, and DC loop gain is 0.61 × 10 = 6.1 versus 10 - a 1.6× loss, far better than the 2.3× loss of pure gain reduction. Add integral action with Ti ≈ 5× the dominant time constant (Ti ≈ 0.5 s ⇒ Ki = Kp/Ti ≈ 1.2) to restore zero steady-state error, accepting the few degrees of lag it costs at crossover.
Anti-windup. During the 200 ms saturated slew at 25% error, the integrator accumulates Ki × e × t = 1.2 × 0.25 × 0.2 = 0.06 V of extra drive-term charge, which must be unwound after the error reverses - that is the source of the exaggerated arrival overshoot. Implement conditional integration / back-calculation: freeze or clamp the integrator whenever the controller output is saturated and the error has the same sign, and initialise the integrator to the drive's present output on entry to saturation. Then verify with a large-step test, not the small-signal step.