Analog Electronics
Analog Electronics on the ESECE tests biasing, small-signal models, op-amp circuits with real imperfections, feedback topologies, and frequency response including stability. Most marks are lost on sign conventions and on mixing large-signal and small-signal thinking in the same calculation.
Biasing and the hybrid-π model
- For a BJT, assume forward-active, solve the base loop for I_B, then I_C = βI_B; verify V_CE > 0.2 V. Voltage-divider bias is stiff when the divider current is at least 10 × I_B.
- g_m = I_C/V_T (≈ 38.5 mS per mA at 300 K), r_π = β/g_m, r_e = V_T/I_E ≈ 26 mV/I_E.
- MOSFET: check V_GS > V_th; saturation needs V_DS > V_GS − V_th, and I_D = ½k_n′(W/L)(V_GS − V_th)²(1 + λV_DS).
Op-amps
Ideal op-amp rules - infinite gain and input impedance, zero output impedance - plus the virtual short hold only inside negative feedback. Non-inverting gain is 1 + R_f/R_g; inverting gain is −R_f/R_in. Real limits: the gain–bandwidth product fixes closed-loop bandwidth at GBW/|A_cl|, slew rate limits the maximum sine frequency to SR/(2πV_pk), and input bias current develops offsets across the source resistance.
Worked example
A common-emitter stage with V_CC = 12 V, R1 = 47 kΩ, R2 = 10 kΩ, R_E = 1 kΩ, R_C = 4.7 kΩ, β = 100. Then V_B = 12 × 10/57 = 2.11 V, V_E = 2.11 − 0.7 = 1.41 V, and I_E = 1.41 mA, so r_e = 26 mV/1.41 mA ≈ 18.4 Ω. With R_E fully bypassed, |A_v| = R_C/r_e = 4700/18.4 ≈ 255 and the stage inverts. Unbypassed, the gain collapses to roughly R_C/(R_E + r_e) ≈ 4.6.
Traps
Dropping the minus sign of the inverting gain; applying the virtual short in positive feedback or open loop; confusing GBW with the unity-gain frequency measured into a specific load; ignoring that a bypass capacitor degenerates the emitter only above the bypass pole; mistaking the Early voltage for a breakdown rating.