Digital Electronics and Logic Design
Digital Electronics and Logic Design tests Boolean minimisation, combinational building blocks, sequential timing, and CMOS implementation. ESECE questions are often short but hinge on one precise definition - a hazard, a setup slack, or a state-encoding detail.
Minimisation and hazards
- Use K-maps or Quine–McCluskey to reach a minimal SOP; don't-care terms are free to include only when they enlarge a group.
- A static-1 hazard appears when two adjacent 1-groups are covered by different product terms. Add the consensus term. Static-0 hazards mirror this in POS form.
- NAND/NOR implementations invert the SOP/POS structure at every level, which changes gate count but not the logic function.
Sequential timing
- Setup and hold define the window around the clock edge; a violation produces metastability, not a logic error you can debug later.
- Setup constraint: T_clk ≥ t_cq + t_comb,max + t_setup + t_skew. Hold constraint: t_cq + t_comb,min ≥ t_hold + t_skew.
- Mealy outputs change with inputs during a cycle (faster, glitchier); Moore outputs decode from state only (safer).
- A mod-N counter needs ⌈log₂N⌉ flip-flops; unused states must be checked or forced into the valid sequence.
Worked example
F(A,B,C) = Σm(0,1,2,3,6,7). Minterms 0–3 give A′ = 1; minterms 6 and 7 give BC = 1. So F = A′ + BC, which is hazard-free across the A′/BC boundary because the bridging term BC is already present. Now the timing check on a path with T_clk = 10 ns, t_cq = 1.5 ns, t_comb = 4.2 ns, t_setup = 1.0 ns and clock skew 0.4 ns: slack = 10 − (1.5 + 4.2 + 1.0) − 0.4 = 2.9 ns, positive, so the path closes.
Traps
Reading a K-map in Gray order but writing the index in binary; forgetting that a redundant consensus term costs area yet removes a hazard; ignoring hold violations caused by too little logic delay; assuming ripple-counter flip-flops all change simultaneously; mixing active-low enables into a state table.