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ESECE: Microprocessors and Embedded Systems

ESECE · Work through your exam, one topic at a time.

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Microprocessors and Embedded Systems

Microprocessors and Embedded Systems tests architecture and timing rather than coding style: addressing modes, memory maps, interrupts, pipelining and hazards, cache behaviour, and the scheduling and volatility issues that bite embedded firmware.

Architecture and addressing

  • Load–store machines such as ARM operate on registers; memory operands need explicit loads. CISC parts such as the 8051 and x86 permit memory operands and richer modes.
  • Addressing modes: immediate, direct/absolute, register indirect, indexed and relative. Register indirect is what makes pointers and stack frames cheap.
  • Endianness: little-endian stores the least significant byte at the lowest address, which matters for network and peripheral buffers.
  • Memory-mapped I/O places peripherals in the address space; volatile stops the compiler caching such a value in a register.

Timing and performance

  • 8051: one machine cycle equals 12 oscillator periods, so a 12 MHz crystal gives 1 µs per machine cycle.
  • Pipelining speed-up is limited by data, control and structural hazards. A 5-stage pipeline has throughput of one instruction per cycle but latency of five.
  • Cache: average access time = hit time + miss rate × miss penalty.

Worked example

8051 at 12 MHz, so one machine cycle is 1 µs. A delay routine uses MOV R2,#200, which takes one machine cycle, and LOOP: DJNZ R2,LOOP, which takes two. The loop executes 200 times, so the total is 1 + 200 × 2 = 401 machine cycles ≈ 401 µs. Doubling the crystal to 24 MHz halves this to about 200 µs, which is why software delays must be re-derived whenever the clock changes.

Interrupts and scheduling

  • An ISR must be short: set a flag or push to a buffer; heavy work belongs in the main loop.
  • Latency equals the current instruction completion plus vector fetch plus context save; nested interrupts need priority and stack depth.
  • In a preemptive RTOS, response depends on priority assignment; priority inversion is bounded by priority inheritance.

Traps

Assuming one machine cycle equals one clock; treating volatile as a memory barrier; ignoring where the reset vector sits; confusing pipeline depth with throughput; writing an ISR that clears the interrupt flag too late and re-enters.