High-Side MOSFET Switch: Thermal Margin After TID and SEGR Derating
A 28 V spacecraft payload uses a P-channel MOSFET as a high-side load switch. The load draws 3.0 A. The selected device has Rds(on) max of 60 mΩ at 25 °C and 110 mΩ at 125 °C, a 150 °C junction limit, Rθjc = 2.0 K/W and Rθcs = 0.5 K/W. The heatsink is 65 K/W in vacuum and 40 K/W in still air. A bench test at 25 °C ambient gives a case temperature of 68 °C. In thermal-vacuum testing with the mounting baseplate at 45 °C, the case stabilizes at 112 °C. The mission total ionizing dose is 30 krad(Si); vendor data show the threshold shifts by up to 0.9 V and Rds(on) rises by 35% at that dose. The gate driver provides 5 V and is rated for the mission. A single-event gate-rupture curve for this device shows a safe drain-source voltage of 28 V only below LET 25 MeV·cm²/mg; the trapped-particle environment includes events above that. The project requires 20 K junction-temperature margin at end of life and a 50% voltage derating for SEE.
1. Calculate the conduction loss and junction temperature in thermal vacuum at beginning of life and at end of life after the stated TID degradation. Does the 20 K end-of-life margin requirement hold?
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Use P = I²R and a thermal path from baseplate to junction.
Beginning of life (BOL): R = 0.110 Ω at 125 °C, so P = 3.0² × 0.110 = 0.99 W. Case temperature = 45 + P(Rθcs + Rθsa) = 45 + 0.99(0.5 + 65) = 45 + 64.8 = 109.8 °C. This is close to the measured 112 °C; the difference is consistent with Rds(on) rising at the actual junction temperature. Junction temperature Tj = 109.8 + P Rθjc = 109.8 + 0.99 × 2.0 = 111.8 °C. Margin to 150 °C is about 38 K.
End of life (EOL): R = 0.110 × 1.35 = 0.1485 Ω, so P = 9 × 0.1485 = 1.337 W. Case temperature = 45 + 1.337(0.5 + 65) = 45 + 87.6 = 132.6 °C. Tj = 132.6 + 1.337 × 2.0 = 135.3 °C. Margin = 150 − 135.3 = 14.7 K.
This is below the required 20 K. Because Rds(on) itself increases with temperature, the true EOL value is slightly worse; iterating with a hot Rds(on) of about 0.155 Ω gives P ≈ 1.40 W and Tj ≈ 137.5 °C, leaving only about 12.5 K. The design therefore fails the EOL margin requirement even though the BOL vacuum case temperature looked acceptable. The bench test at 25 °C in air is not representative: with Rθsa = 40 K/W, case temperature would be about 25 + 0.99(40.5) = 65 °C, matching the 68 °C observation, but vacuum removes convection and raises the heatsink resistance sharply.
2. Assess whether the 5 V gate drive remains adequate after the threshold shift. What additional MOSFET or driver data would you require before accepting the part?
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The 5 V drive must guarantee sufficient gate-source overdrive at the worst-case EOL threshold and at Tj ≈ 135 °C. If the initial |Vth| is 1.5 V and the radiation-induced shift is 0.9 V in the direction that makes the P-channel device harder to enhance, then |Vth| ≈ 2.4 V and the overdrive is only 5 − 2.4 = 2.6 V. The specified Rds(on) is usually measured at a higher Vgs, so the 110 mΩ and the +35% TID degradation may not be valid at 2.6 V overdrive. The part could be much hotter than the calculation predicts.
The direction of the threshold shift matters. For a P-channel device, a negative shift makes turn-on harder and raises conduction loss; a positive shift can increase off-state leakage or unwanted turn-on. The design must bound both directions, not just the magnitude. I would require: Rds(on) versus Vgs curves at 5 V and at 135 °C; the threshold-shift distribution and direction from biased irradiation; gate leakage and drain-source leakage at EOL; and confirmation that the driver's 5 V output is maintained over its own TID and temperature range. If the overdrive is inadequate, use a 10 V drive with a charge pump or select a logic-level FET characterized at 5 V and 135 °C. The gate resistor and Miller charge also need checking for turn-off transient and single-event transient immunity.
3. Evaluate the single-event gate-rupture situation. The bus is 28 V and the device is rated 60 V Vds, so a simple 50% voltage derating is met. Is that sufficient? Recommend a disposition.
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No. The 50% voltage derating is a DC stress rule and does not guarantee SEGR immunity. The SEGR safe-operating-area curve says that at Vds = 28 V the device is safe only below LET 25 MeV·cm²/mg, while the environment contains events above that. The part is therefore outside its SEGR SOA at the actual bus voltage, even though 28 V is less than 50% of 60 V.
A defensible disposition has three parts. First, select a MOSFET whose SEGR LET threshold at 28 V exceeds the environment's worst-case LET with margin, or whose rated Vds is high enough that the 28 V operating point sits well inside the tested SOA. Second, add a drain-source clamp or transient suppressor so that inductive turn-off and harness transients cannot push Vds above the tested safe value; SEGR risk rises sharply with applied Vds. Third, add current limiting and, if practicable, redundancy or a series switch that can isolate the load after a fault. The radiation lot acceptance test should be at the actual bus voltage, temperature, and gate bias, because SEGR thresholds are bias- and temperature-dependent. A simple derating calculation alone is not acceptable evidence for flight.