ISRO Scientist/Engineer SC (Electronics) study materials
ISRO Scientist/Engineer SC (Electronics) study resources

ISRO Scientist/Engineer SC (Electronics) study plan

ISRO Scientist/Engineer SC (Electronics) · Give each week a clear focus.

8 weeks · About 7 hours per week

Week 1

Electronic Devices and Circuits & Analog Circuits

  • Derive and sketch the DC load line, transconductance, and small-signal voltage gain for BJT CE, CB, CC and MOSFET CS, CG, CD amplifiers from a single set of bias equations, and tabulate the input/output resistance of each configuration.

  • Solve 25 numericals on diode circuits covering Zener regulation, clipper/clamper, and rectifier ripple factor and PIV, recording every mistake by error type.

  • Compute the hybrid-pi and hybrid-pi high-frequency cutoff (fT, Miller effect) for two transistor stages and state in writing why the Miller capacitance dominates bandwidth.

  • Build a one-page formula sheet for Domain 1 covering pn junction, BJT Ebers-Moll, MOSFET regions of operation, and thermal runaway.

  • Explain in a short written note how feedback (series-shunt, shunt-shunt) changes input/output resistance and bandwidth, with one numeric example each.

Your checkpoint

A 40-question self-made quiz on Domains 1 and 2, attempted closed-book with a scored answer key and a list of the five weakest concepts.

Week 2

Electronic Devices and Circuits & Analog Circuits

  • Analyze op-amp circuits (inverting, non-inverting, integrator, differentiator, instrumentation amplifier, precision rectifier) and compute gain, offset error, and CMRR effects for each.

  • Design and numerically verify a Wien-bridge oscillator for 5 kHz and a phase-shift oscillator for 2 kHz, stating the Barkhausen condition explicitly.

  • Compute loop gain, closed-loop gain, and phase margin for a given op-amp with a two-pole open-loop response, and determine the compensation capacitor value needed for 60 degrees phase margin.

  • Work through 20 problems on active filters (Sallen-Key low-pass and high-pass, second-order Butterworth) and verify cutoff and Q by hand.

  • Summarize power amplifier classes A, B, AB, and C with efficiency derivations and crossover distortion mitigation.

Your checkpoint

A worked solutions notebook of 30 mixed analog problems (op-amps, oscillators, filters, power amplifiers) with hand-checked numerical answers.

Week 3

Digital Electronics and Logic Design & Computer Organization and Networks

  • Design combinational blocks (4-bit carry-lookahead adder, 4:1 mux realization of a Boolean function, BCD-to-seven-segment decoder) from truth table to gate-level netlist.

  • Minimize five Boolean functions using Karnaugh maps and verify each with Quine-McCluskey, documenting the prime implicants.

  • Analyze sequential circuits: derive state tables and state diagrams for JK and D flip-flop based counters, and design a mod-6 synchronous counter with a specified state encoding.

  • Compute setup, hold, and clock-to-Q timing margins for a two-flop path with given delays and identify the maximum clock frequency.

  • Explain static and dynamic hazards, and design a hazard-free implementation of one Boolean expression.

Your checkpoint

A complete design document for a 4-bit synchronous up/down counter with seven-segment display, including state diagram, K-maps, gate netlist, and timing-margin calculation.

Week 4

Digital Electronics and Logic Design & Microprocessors, Microcontrollers and Embedded Systems

  • Write and hand-trace 8085 and 8051 assembly programs for block addition, data transfer, and delay loops, counting instruction cycles for each.

  • Map the 8085 memory and I/O space for a given address decoding scheme and compute chip-select ranges for 2 KB and 4 KB EPROM/RAM.

  • Describe 8051 timer modes, serial port modes, and interrupt vector table, and configure Timer 0 in mode 2 for a stated baud rate with the reload value computed.

  • Compare memory-mapped and I/O-mapped addressing and identify which peripherals in a given system map where.

  • Explain pipelining, cache mapping (direct, set-associative), and the difference between RISC and CISC with one concrete example each.

Your checkpoint

A timed 90-minute mock test of 30 questions across Domains 3, 8, and 9, scored with a written error analysis of every wrong answer.

Week 5

Signals and Systems & Communication Systems (Analog and Digital)

  • Classify signals by energy/power and compute energy and power spectral density for standard pulses, and state the conditions for a system to be LTI, causal, and BIBO stable.

  • Compute the Fourier series and Fourier transform of rectangular, triangular, and exponential signals, and apply Parseval's theorem to two numericals.

  • Apply the sampling theorem: compute the Nyquist rate, design an anti-aliasing filter, and explain quantization noise and SNR for an n-bit PCM system with a worked example.

  • Analyze LTI systems using Laplace and z-transforms, determine ROC, and check stability from pole locations for five given transfer functions.

  • Derive the convolution of two rectangular pulses graphically and verify the result by transform-domain multiplication.

Your checkpoint

A one-page-per-topic summary set (five pages) on Fourier, Laplace, z-transform, sampling, and convolution, each with one fully solved numerical.

Week 6

Communication Systems (Analog and Digital) & Electromagnetics, Antennas and Microwave Engineering

  • Compute AM, DSB-SC, SSB, and FM modulation index, bandwidth, and power efficiency for given parameters, and compare noise performance of AM and FM with derivations.

  • Design a superheterodyne receiver: select IF, compute image frequency, and explain image rejection and AGC.

  • Compute link budget for a satellite downlink: EIRP, free-space path loss, G/T, and C/N0, using given values.

  • Apply the Friis transmission equation and derive the radar range equation, then compute maximum detection range for a stated target RCS.

  • Explain PCM, PSK, QPSK, and 16-QAM constellations, compute bit error rate trends versus Eb/N0 qualitatively, and state bandwidth efficiency for each.

Your checkpoint

A solved problem set of 25 communication numericals (modulation, noise, link budget, BER) with all intermediate values shown.

Week 7

Electromagnetics, Antennas and Microwave Engineering & Control Systems

  • Derive Maxwell's equations in differential and integral form and apply them to plane-wave propagation in free space and a lossy dielectric, computing skin depth and attenuation.

  • Compute characteristic impedance, reflection coefficient, VSWR, and stub matching for a 50-ohm line terminated in a complex load using the Smith chart by hand.

  • Design a rectangular microstrip patch antenna for a stated frequency and substrate, computing patch dimensions and feed-point impedance approximately.

  • Analyze first- and second-order control systems: compute damping ratio, natural frequency, rise time, settling time, and steady-state error for step, ramp, and parabolic inputs.

  • Apply Routh-Hurwitz and Nyquist criteria to determine stability and gain margin of three given open-loop transfer functions.

Your checkpoint

A hand-drawn Smith chart solution for two matching problems plus a stability analysis sheet for three systems, both checked against analytical calculations.

Week 8

Instrumentation, Measurements and Spacecraft Electronics & Control Systems

  • Explain the working of strain gauges, LVDTs, thermocouples, and Hall sensors, and compute bridge sensitivity and error for a given measurement setup.

  • Analyze a data acquisition chain: signal conditioning, anti-alias filtering, ADC resolution, and error budget, with a worked numerical.

  • Describe spacecraft power, telemetry, and telecommand subsystems and the role of redundancy and radiation tolerance at block-diagram level.

  • Tune a PID controller for a given plant using Ziegler-Nichols and verify the closed-loop response by computing phase margin.

  • Complete two full-length timed mock tests of 60 questions each under exam conditions and log every weak topic.

Your checkpoint

A consolidated error log from both mock tests plus a final one-page revision sheet per domain, with a ranked list of the ten weakest topics and a plan for the remaining revision days.

Milestones

Week 2: Score at least 65% on the self-made Domain 1 and 2 quiz closed-book, and be able to derive the small-signal gain of all six single-transistor configurations from memory within 10 minutes.

Week 4: Score at least 60% on the 30-question mock across Domains 3, 8, and 9, and correctly design a mod-6 counter and compute a setup/hold timing margin without notes.

Week 6: Score at least 60% on the 25-question communication numerical set and complete a satellite link budget end-to-end with no formula sheet.

Week 8: Score at least 70% on both full-length 60-question mocks and be able to state the five weakest topics with a concrete revision action for each.