ISRO Scientist/Engineer SC (Electronics) flashcards

40 cards. Read the term and the definition here. The deck at the top of this page is optional.

Diode equation

Shockley diode equation I = I_s(e^(V/(nV_T))−1) models PN junction current; V_T ≈ 26 mV at room temperature and n is ideality factor.

BJT alpha and beta

α = I_C/I_E and β = I_C/I_B; relationship α = β/(β+1) and β = α/(1−α). Typical β 50–300, α close to unity.

MOSFET saturation condition

MOSFET operates in saturation when V_DS ≥ V_GS − V_th; drain current approximately ½ μ_n C_ox (W/L)(V_GS−V_th)²(1+λV_DS).

Zener regulator design

Series resistor R = (V_in − V_Z)/(I_Z + I_L) keeps Zener in reverse breakdown; I_Z must exceed knee current at minimum input and full load.

Op-amp virtual short

With negative feedback and ideal op-amp, differential input voltage is zero: V₊ = V₋; input current is zero, enabling node equations.

Barkhausen criterion

Oscillator sustains oscillation when loop gain magnitude |Aβ| equals one and total loop phase shift is 0° or 360° at oscillation frequency.

Class B efficiency

Complementary push-pull Class B amplifier maximum theoretical efficiency is π/4 ≈ 78.5%; crossover distortion reduced in Class AB by bias.

Instrumentation amplifier CMRR

Three-op-amp instrumentation amplifier rejects common-mode noise; CMRR depends on resistor matching and typically exceeds 100 dB for low-level sensor signals.

Karnaugh map grouping

Adjacent 1-cells in powers of two (1,2,4,8,16) are grouped to minimize SOP expressions; don't-care cells may be included to enlarge groups.

Setup and hold time

Flip-flop data must be stable t_su before and t_h after active clock edge; violations cause metastability, mitigated by synchronizer flip-flops.

Race-around condition

In JK flip-flop, if clock pulse width exceeds 2t_pd, output toggles repeatedly; master-slave JK configuration eliminates race-around by edge triggering.

CMOS dynamic power

Dynamic power P = α C V_DD² f, where α is switching activity, C load capacitance, V_DD supply, f clock frequency; static power negligible.

Sampling theorem

A bandlimited signal with maximum frequency f_max can be reconstructed if sampled at f_s > 2f_max; otherwise aliasing occurs and information is lost.

LTI BIBO stability

Continuous LTI system is BIBO stable if all poles lie in left half s-plane; discrete system if all poles lie inside unit circle in z-plane.

DFT and FFT

DFT X[k] = Σ x[n]e^(−j2πkn/N) maps N samples to frequency bins; FFT algorithm reduces computation from O(N²) to O(N log₂ N).

Group delay

Group delay τ_g = −dφ(ω)/dω measures envelope delay through a system; constant group delay indicates linear phase and no dispersion.

AM modulation index

μ = A_m/A_c for amplitude modulation; μ ≤ 1 avoids overmodulation; total power P_t = P_c(1 + μ²/2) and efficiency μ²/(2+μ²).

Carson's rule

FM bandwidth estimate B ≈ 2(Δf + f_m), where Δf is peak frequency deviation and f_m is highest modulating frequency; valid for wideband FM.

Shannon channel capacity

C = B log₂(1 + S/N) bits per second gives maximum error-free rate over AWGN channel with bandwidth B and signal-to-noise ratio S/N.

PCM quantization SNR

For full-scale sinusoid, quantization SNR ≈ 6.02n + 1.76 dB with n bits per sample; each additional bit improves SNR by about 6 dB.

Poynting vector

S = E × H gives instantaneous power density (W/m²); time-average is ½ Re(E × H*) for time-harmonic fields; direction of energy flow.

Transmission line Z0

Characteristic impedance Z₀ = √(L/C) for lossless line; propagation velocity v = 1/√(LC); reflection coefficient Γ = (Z_L−Z₀)/(Z_L+Z₀).

VSWR and return loss

VSWR = (1+|Γ|)/(1−|Γ|); return loss RL = −20 log₁₀|Γ| dB. Matched load gives Γ = 0, VSWR = 1, infinite return loss.

Half-wave dipole

Center-fed dipole of length λ/2 has input impedance ≈ 73 + j42.5 Ω, directivity 1.64 (2.15 dBi), and half-power beamwidth about 78°.

Friis transmission equation

P_r/P_t = G_t G_r (λ/(4πR))² for free-space line-of-sight link; received power falls with square of distance and square of frequency.

Rectangular waveguide cutoff

Cutoff frequency f_c = (c/2)√((m/a)² + (n/b)²); dominant TE₁₀ mode has f_c = c/(2a) for broad wall dimension a.

Radar range equation

R_max = [(P_t G² λ² σ)/((4π)³ P_min)]^(1/4); depends on transmit power, antenna gain, target cross section, and minimum detectable signal.

Second-order overshoot

Percent overshoot %OS = 100 e^(−ζπ/√(1−ζ²)) for underdamped second-order system; depends only on damping ratio ζ.

Routh-Hurwitz criterion

Number of sign changes in first column of Routh array equals number of closed-loop poles in right half-plane; necessary condition all coefficients positive.

Bode gain margin

Gain margin = −20 log|G(jω_pc)| where phase crossover frequency ω_pc gives ∠G = −180°; positive margin indicates stable closed-loop system.

PID controller terms

Proportional K_p e, integral K_i ∫e dt eliminates steady-state error, derivative K_d de/dt adds damping; tuned by Ziegler-Nichols or root locus.

8085 microprocessor

8-bit Intel microprocessor with 16-bit address bus, 8-bit data bus, 3 MHz clock, registers A, B, C, D, E, H, L, SP, PC, and 40-pin DIP package.

8051 microcontroller

8-bit MCU with 4 KB ROM, 128 bytes RAM, 32 I/O lines, two 16-bit timers, full-duplex UART, and five interrupt sources; Harvard architecture.

Watchdog timer

Hardware timer that resets MCU if firmware fails to refresh it within timeout; independent clock source improves reliability in embedded systems.

Cache miss penalty

Average memory access time = hit time + miss rate × miss penalty; reducing miss rate or penalty improves processor performance.

TCP versus UDP

TCP is connection-oriented and reliable with flow and congestion control; UDP is connectionless, lower latency, used for streaming and DNS queries.

Amdahl's law

Speedup = 1/((1−f) + f/s) where f is fraction enhanced and s is speedup of that fraction; serial portion limits overall gain.

Wheatstone bridge balance

Bridge balanced when R₁/R₂ = R₃/R₄; null detector reads zero; used with strain gauges, RTDs, and other resistive transducers.

ADC quantization error

Ideal ADC quantization error is ±½ LSB; LSB = V_ref/2^n; SNR for full-scale sine ≈ 6.02n + 1.76 dB with n bits.

Single-event upset

SEU is a radiation-induced bit flip in memory or logic; mitigated by error-detecting and correcting codes, shielding, and latch-up immune processes.