Computer Organization and Networks
Computer Organization and Networks tests the CPU datapath, memory hierarchy, pipelining and the networking stack from framing to subnetting.
Core rules
- Pipeline speedup is limited by the slowest stage plus overhead; ideal speedup ≈ number of stages, reduced by hazards and stalls.
- Cache: AMAT = hit time + miss rate × miss penalty. Write-through keeps memory coherent; write-back reduces traffic. Direct-mapped, set-associative and fully associative caches differ in conflict misses.
- Locality explains cache behaviour; larger blocks help spatial locality but can hurt if blocks become too large.
- Networking: OSI layers map to TCP/IP layers. TCP is connection-oriented with sliding window and congestion control; UDP is connectionless.
- IPv4 subnetting: a /n prefix leaves 32−n host bits; usable hosts = 2^(32−n)−2.
- ARQ: stop-and-wait efficiency = 1/(1+2a), where a is propagation delay divided by transmission time; sliding window improves utilisation.
Worked example
A cache has 1-cycle hit time, 5% miss rate and 20-cycle miss penalty. AMAT = 1 + 0.05×20 = 2 cycles. If the miss rate is halved to 2.5%, AMAT becomes 1 + 0.025×20 = 1.5 cycles, a 25% reduction. This shows why reducing misses matters more than shaving hit time once the hit path is already short. For 192.168.10.0/26, the mask is 255.255.255.192, giving 4 subnets and 62 usable hosts each; the subnets are .0, .64, .128 and .192.
Traps
- Counting network and broadcast addresses as usable.
- Using the wrong mask when the prefix is not a multiple of 8.
- Assuming pipeline speedup equals stage count when stalls exist.
- Confusing write-allocate with write-through.
- Mixing TCP port numbers with IP addresses.