Digital Electronics and Logic Design
Digital Electronics and Logic Design tests Boolean minimisation, combinational building blocks, sequential timing and CMOS implementation. ISRO questions often combine a K-map with a timing or fan-out constraint.
Core rules
- Boolean identities: X + X'Y = X + Y; consensus XY + X'Z + YZ = XY + X'Z.
- K-map groups are powers of two, wrap around edges, and should be as large as possible; don't-care terms may be used but are not required.
- Combinational blocks: multiplexer as universal logic, decoder as minterm generator, carry look-ahead reduces ripple delay.
- Flip-flops: setup and hold windows must be met; propagation delay plus routing must fit the clock period. Metastability occurs when data changes inside the aperture.
- Synchronous design uses one clock; asynchronous inputs need synchronisers.
- CMOS static power is low; dynamic power ≈ αCV²f; propagation delay rises with load capacitance.
Worked example
Minimise F(A,B,C) = Σm(0,1,2,5,6,7). K-map groups: m0,m1 → A'B'; m2,m6 → BC'; m5,m7 → AC. All six minterms are covered, so F = A'B' + BC' + AC. Check m5 = 101: A'B'=0, BC'=0, AC=1, so F=1. Check m3 = 011: all terms 0, so F=0. The cover is minimal in literal count for this grouping.
Traps
- Making overlapping groups that fail to cover a minterm.
- Forgetting that setup time is before the clock edge and hold time after.
- Assuming a ripple counter is synchronous.
- Ignoring clock skew, which eats timing margin.
- Confusing active-low enable polarity.