IESL Part II Electrical cheat sheet

Per-unit (pu) system: Z_pu = Z_actual / Z_base, Z_base = V_base² / S_base; for transformers, per-unit impedance is the same on either side when bases are chosen in the winding ratio, so pu values transfer directly across the transformer.

Symmetrical components: positive/negative/zero sequence with a = 1∠120°; I0 = (Ia + Ib + Ic)/3. Zero-sequence current needs a return path - it is blocked by delta windings and by ungrounded neutrals, which is the basis of most grounding and protection questions.

Three-phase fault levels: I_fault(pu) = 1 / Z_th(pu); I_base = S_base / (√3 · V_base). Fault MVA = S_base / Z_pu. For a line-to-ground fault, I_LG = 3·V_phase / (Z1 + Z2 + Z0).

Transmission line models: short line (<80 km) uses series R + jX; medium line uses nominal-π or nominal-T with shunt admittance; long line uses hyperbolic ABCD constants: A = D = cosh γl, B = Z_c sinh γl, C = sinh γl / Z_c, with γ = √(zy) and Z_c = √(z/y).

Surge impedance loading (SIL) = V_L² / Z_c; for overhead lines Z_c ≈ 400 Ω, so SIL ≈ V_L²/400 MW (V_L in kV). A line loaded below SIL is net capacitive; above SIL it is net inductive - this drives Ferranti rise on light load.

Induction motor torque-speed: synchronous speed Ns = 120f/p; slip s = (Ns − Nr)/Ns. Torque ∝ V², and starting torque/current scale directly with rotor resistance - deep-bar and double-cage rotors exploit skin effect to raise starting torque without wrecking full-load efficiency.

Transformer parallel operation requires the same polarity, same voltage ratio, same phase-sequence/vector group, and comparable per-unit impedance; circulating current flows if ratios or vector groups mismatch, and load shares in inverse proportion to per-unit impedance.

Protection coordination: IDMT relay time t = TMS · k / ((I/Is)^α − 1) (IEC curve constants, e.g. standard inverse k = 0.14, α = 0.02). Current transformers must not be open-circuited on the secondary (dangerous voltage), and CT saturation during DC offset can cause differential relay maloperation unless it is biased.

Cable and conductor sizing: continuous current rating is derated by ambient temperature, soil thermal resistivity, grouping, and depth factors; voltage drop ≈ √3 · I · (R cos φ + X sin φ) for three-phase. Short-circuit withstand follows the adiabatic rule S ≥ I_sc · √t / k.

BJT regions: cutoff (both junctions off), active (BE forward, BC reverse - used for amplification), saturation (both forward - used as a switch). For a silicon device V_BE ≈ 0.7 V in conduction; β = I_C/I_B and I_E = (β+1)I_B.

MOSFET: in saturation (the amplifier region) I_D = ½ μ_n C_ox (W/L)(V_GS − V_th)², requiring V_DS > V_GS − V_th. In triode it behaves as a voltage-controlled resistor. CMOS static power is essentially leakage only; dynamic power = α C V_DD² f.

Op-amp ideal rules: no input current, V+ = V− under negative feedback. Inverting gain = −R_f/R_in; non-inverting gain = 1 + R_f/R_g; integrator/differentiator swap R and C. Slew rate limits full-power bandwidth: f_max = SR / (2π V_peak).

Sampling: Nyquist requires f_s > 2·f_max; aliasing folds components to |f − k·f_s|. An anti-alias filter must precede the sampler. Quantization SNR for a full-scale sine ≈ 6.02N + 1.76 dB for an N-bit converter.

LTI systems: output is the convolution of input with impulse response; in the Laplace domain H(s) = Y(s)/X(s), and stability requires all poles in the left half-plane. A first-order RC low-pass has cutoff f_c = 1/(2πRC) and −20 dB/decade roll-off.

Digital logic: NAND and NOR are functionally complete; De Morgan's laws ¬(A·B) = ¬A + ¬B and ¬(A+B) = ¬A·¬B. A JK flip-flop toggles when J = K = 1; a D flip-flop samples D on the clock edge and is the standard register element.

Modulation: AM bandwidth = 2f_m and total power P_t = P_c(1 + m²/2); DSB-SC and SSB suppress the carrier. FM has constant envelope (immune to amplitude noise) but needs wide bandwidth per Carson's rule B ≈ 2(Δf + f_m).

Noise and link budget: thermal noise power N = kTB (k = 1.38×10⁻²³ J/K), so −174 dBm/Hz at 290 K. Shannon capacity C = B log₂(1 + S/N). Free-space path loss in dB = 32.45 + 20log₁₀(d_km) + 20log₁₀(f_MHz).

Transmission lines and matching: reflection coefficient Γ = (Z_L − Z_0)/(Z_L + Z_0), VSWR = (1+|Γ|)/(1−|Γ|). A quarter-wave transformer of impedance √(Z_0 Z_L) matches a real load; a shorted quarter-wave stub presents an open circuit.