IESL Part II Electrical study plan

Build a one-page formula sheet covering circuit laws, phasor analysis, and three-phase power, writing each formula from memory before checking it against a textbook

Solve 20 problems on network theorems (Thevenin, Norton, superposition, maximum power transfer) and log every error with its root cause

Derive the conditions for series and parallel resonance and compute bandwidth and quality factor for at least five numeric cases

Draw and label the full per-phase equivalent circuit for a balanced three-phase star and delta load, then compute line and phase quantities for two worked examples

Compute magnetic flux, reluctance, and inductance for series and parallel magnetic circuits, including one case with an air gap

Explain and calculate the operation of a single-phase transformer using its equivalent circuit, referring primary quantities to the secondary side

Compare the torque-speed characteristics of induction and synchronous machines and state how slip is calculated

Solve 15 problems on DC machines and three-phase induction motors covering efficiency, losses, and starting methods

Analyse a balanced and an unbalanced three-phase fault using per-unit quantities on a chosen base

Rank the standard protection devices (overcurrent, differential, distance, earth fault) by the fault types they cover and justify each choice

Calculate the earthing requirements and touch and step voltage limits for a stated installation scenario

Interpret the key clauses of an electrical installation standard on protective conductor sizing and disconnection times

Design and analyse a full-wave rectifier with a capacitor filter, computing ripple voltage and diode peak inverse voltage

Bias a BJT in common-emitter configuration and determine the operating point graphically and by calculation

Derive the closed-loop gain and bandwidth of an ideal op-amp in inverting, non-inverting, and integrator configurations

Solve 12 problems on diode, BJT, and op-amp circuits under timed conditions

Convert between binary, hexadecimal, and BCD and perform two's-complement arithmetic on signed numbers

Minimise a five-variable Boolean function using Karnaugh maps and verify the result with De Morgan's laws

Design a synchronous counter and a state machine from a state diagram, including the excitation table

Compare the characteristics of common logic families (TTL, CMOS) on fan-out, noise margin, and power dissipation

Calculate the bandwidth, signal-to-noise ratio, and channel capacity of analogue and digital modulation schemes (AM, FM, ASK, FSK, PSK, QAM)

Explain sampling theory, quantisation error, and companding, and compute the bit rate for a given PCM system

Describe the OSI and TCP/IP layered models and place at least ten named protocols in the correct layer

Solve 10 problems on modulation, noise, and link budget, including one free-space path loss calculation

Assemble a single master revision sheet condensing all earlier formula sheets into no more than four pages

Re-solve every item in the error log from weeks 1 to 6 without consulting notes and mark those still failing

Complete two full-length mock papers under exam timing and record the score for each domain

Identify the three weakest sub-topics from the mock results and write a targeted remediation list for each

Remediate the three weakest sub-topics identified in week 7 by solving 10 new problems in each

Rehearse the master revision sheet from memory in under 30 minutes and correct any gaps

Complete one final full-length mock paper and aim for a score at least 10 percentage points above the week-7 average

Plan the exam-day logistics: permitted references, calculator, timing strategy, and question order