EGEL Plus Ingeniería Electrónica common mistakes
EGEL Plus Ingeniería Electrónica · Understand the traps and how to avoid them.
Resolving op-amp circuits with ideal assumptions (infinite gain, zero input current, zero offset) and then choosing the answer that ignores finite gain, input bias current, and slew-rate limits, even when the item states a gain-bandwidth product or a supply voltage.
Most candidates study the ideal op-amp model first and never drill the non-ideal parameters under exam pressure; the ideal answer is usually among the distractors, so it feels correct and confirms the error.
What to do instead
Before computing, list the non-ideal parameters given in the stem (GBW, SR, Ib, Vos, rails) and check each one against the result: closed-loop bandwidth = GBW/β, maximum sine frequency from slew rate = SR/(2πVp), output swing against rails. Practice 10 items where the ideal answer is a trap and the correct one requires one non-ideal correction.
Analyzing a transistor bias network or amplifier by memorizing a formula (e.g., fixed β-based collector current) instead of first establishing the operating region and using the correct model for that region.
Textbook formulas are often derived for the active/saturation region; candidates apply them to circuits that are actually in cutoff or triode/saturation and get plausible but wrong numbers.
What to do instead
Adopt a fixed routine: assume a region, solve, then verify the assumption (VCE > 0.3 V for active, VDS > VGS − VTH for saturation). If verification fails, re-solve with the other model. Do at least five bias problems where the initial assumption is wrong.
Designing combinational or sequential logic without a complete truth table or next-state table, then guessing at don't-care conditions and producing a circuit that fails for the unlisted input combinations.
Time pressure pushes candidates to jump from the verbal description straight to a Karnaugh map or a flip-flop excitation table, skipping the enumeration step where most of the reasoning actually lives.
What to do instead
Always write the full truth/state table first, explicitly mark don't-cares, then minimize. For sequential items, build the state diagram, assign states, derive the excitation inputs for the chosen flip-flop (D, JK, or T), and verify by simulating two input sequences by hand.
Ignoring timing and resource constraints in embedded items: choosing a polling loop or delay-based timing for a task that the stem says must be deterministic, or sizing a timer/counter without checking prescaler and overflow.
Candidates focus on functional correctness and treat timing, interrupts, and memory footprint as secondary, even though the item explicitly frames the requirement around them.
What to do instead
For every embedded item, extract the constraint words (deterministic, low power, real-time, limited RAM) and eliminate any option that violates them before comparing features. Rehearse timer calculations: count = t·f_clk/prescaler, and check that the count fits the timer width.
Treating an instrumentation chain as independent blocks and adding or ignoring error sources incorrectly: summing gain errors and offset errors without RSS, forgetting sensor sensitivity and bridge excitation, or omitting CMRR and noise contributions of the amplifier.
Candidates learn each block in isolation and rarely practice end-to-end error budgets, so they default to simple addition or to ignoring a term entirely.
What to do instead
Build a one-page error budget template: convert every error to input-referred units (offset, drift, gain error, CMRR-induced offset = Vcm/CMRR, noise in RMS), combine random terms by root-sum-square and systematic terms linearly, then refer to output. Practice with a Wheatstone bridge plus instrumentation amplifier and a thermocouple plus cold-junction case.
Selecting a sensor or conditioning circuit by resolution alone, ignoring range, linearity, response time, and environmental effects stated in the stem (temperature drift, self-heating, lead resistance).
Resolution is the most visible specification and the one most emphasized in study material, so it dominates the decision and the other constraints get discounted.
What to do instead
Rank the constraints in the stem before looking at options, then check each candidate against all of them. Specifically drill: 2-wire vs 4-wire RTD lead-resistance error, thermistor linearization, and ADC effective resolution versus SNR (ENOB = (SNR − 1.76)/6.02).
Answering control-system items by inspecting the transfer function qualitatively (poles left or right) without computing steady-state error, phase margin, or stability margins for the specific loop gain given.
Qualitative rules are quick and often sufficient for simple items, but exam items usually hinge on a numeric margin or a specific error constant that the qualitative shortcut cannot supply.
What to do instead
For each item, identify the requested quantity and compute it: type number and error constants for steady-state error, Routh-Hurwitz or Bode margins for stability, and root-locus rules for pole movement. Verify with a quick Bode sketch and state the margin in degrees or dB rather than 'stable/unstable'.
Confusing automation-layer concepts: mixing PLC scan-cycle behavior with hardwired relay logic, assigning fieldbus or industrial protocol roles incorrectly, or choosing a control architecture without checking the required response time and safety function.
These topics are often learned from product literature rather than from first principles, so the vocabulary is familiar but the operational distinctions are fuzzy.
What to do instead
Make a comparison table for scan cycle vs interrupt vs event-driven execution, and for the industrial protocols you may see (Modbus, Profibus, EtherCAT, CANopen) covering topology, determinism, and typical cycle time. For each architecture item, first write the required response time and safety integrity level, then eliminate options that cannot meet them.
Applying an OSI-layer or addressing rule to the wrong layer: attributing routing or fragmentation to Layer 2, treating a switch as a broadcast-domain boundary, or computing subnet ranges without accounting for network and broadcast addresses.
Candidates memorize layer names but not the operational consequences, and subnetting is often practiced only with easy masks, so the boundary cases are shaky.
What to do instead
For every networking item, name the layer and the PDU before answering. Drill subnetting with non-/24 masks: compute network address, broadcast, usable host count (2^h − 2), and verify by converting to binary. Build a one-page table of which device or protocol operates at which layer.
Skipping the professional-practice items (ethics, standards, project management) because they look like common sense, and answering from intuition rather than from the applicable norm or contractual obligation described in the stem.
Candidates over-invest in technical calculation and treat these items as free points, but the correct option usually depends on a specific standard, code of ethics, or project constraint stated in the scenario.
What to do instead
Read these items last but read them fully: identify the role (employee, manager, consultant), the obligation at stake (confidentiality, conflict of interest, safety, regulatory compliance), and the constraint (scope, schedule, cost). Answer the option that satisfies the stated obligation with the least harm and the proper escalation path, not the most convenient one.