Asynchronous FIFO Overflow With Bounded Read Stalls
An FPGA design writes 16-bit samples into an asynchronous FIFO at 100 MHz in bursts of 64 words, one word per clock. The read side runs at 125 MHz but occasionally stalls for 20 read-clock cycles while a shared memory controller services another master. The FIFO uses Gray-coded pointers and a two-flop synchronizer. The current FIFO depth is 16 words, and the almost-full flag asserts at 12 words. During stress testing, the design reports occasional overflow. The write side cannot be throttled without violating the 100 MHz sample rate, and the read-side stall is bounded and known. The synchronization latency is two read-clock cycles in each direction. The system must never drop a sample. No clock-domain crossing tool has been run yet.
1. Compute the worst-case FIFO occupancy caused by a 20-cycle read stall and decide whether a 16-word FIFO is sufficient.
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The read clock period is 1/125 MHz = 8 ns, so a 20-cycle stall lasts 160 ns. During that time the write side at 100 MHz produces 160 ns / 10 ns = 16 words. The read side consumes nothing during the stall. Therefore the stall alone can add 16 words of backlog. Add synchronization latency: the write pointer takes about two read clocks to appear on the read side, and the read pointer takes about two write clocks to appear on the write side. That can add several words of uncertainty, especially if the stall begins just after a pointer sample. A 16-word FIFO with almost-full at 12 words is therefore not sufficient; it can overflow even before accounting for all synchronization uncertainty. The observed overflow is consistent with this calculation.
2. Recommend a FIFO depth and explain how the almost-full threshold should be set.
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Use at least 32 words, and preferably 64 words if block RAM allows. The 20-cycle stall contributes 16 words, and the two-flop synchronizers plus Gray-code pointer sampling add several words of worst-case uncertainty. A 32-word FIFO leaves margin for the stall plus synchronization latency while still fitting small block RAM. Set almost-full so the write side can react before the true full point; with a 32-word FIFO, asserting almost-full at 24 words is reasonable if the write side can stop within a few cycles. However, the problem states the write side cannot be throttled, so the FIFO must absorb the entire bounded burst. Do not rely on almost-full as the primary protection; size the FIFO for the worst-case occupancy and use almost-full as a diagnostic.
3. What CDC verification would you require before signing off the design?
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Run a CDC lint or formal check on the Gray-coded pointers and confirm that only one bit changes per source-clock transition. Verify that the two-flop synchronizers are placed and constrained correctly, with no false paths that remove the required timing exceptions. Simulate worst-case read stalls aligned to the start, middle, and end of the 64-word burst, including pointer synchronization latency. Use an assertion that flags write-when-full and read-when-empty, and run it for long random stress with the bounded stall injected. Also confirm reset behavior and that the almost-full flag is not used as the sole overflow protection. The design should never drop a sample under the specified stall bound.