FE Electrical & Computer common mistakes
FE Electrical & Computer · Understand the traps and how to avoid them.
On NCEES-supplied reference questions, the candidate recalculates a quantity from first principles using a memorized formula instead of reading the value or relationship directly from the provided tables (unit conversions, wire ampacity, conduit fill, Laplace transforms).
Candidates treat the exam as closed-book and drill formulas from textbooks, so under time pressure they reconstruct a conversion factor from memory rather than flipping to the supplied table, and a misremembered factor silently corrupts every downstream step.
What to do instead
During practice, work every problem with the actual NCEES reference handbook open beside you and mark which table you used. Build a personal index of the handbook sections you touch most (conversions, motor tables, transform pairs) so lookup becomes a reflex rather than a last resort.
On per-unit and three-phase power problems, the candidate mixes line-to-line and line-to-neutral voltages, or forgets to convert the base impedance when changing the MVA base between transformer stages.
Per-unit work is taught with formulas that hide the sqrt(3) and the base-change ratio; candidates memorize S = VI without tracking whether V is line or phase, and the arithmetic looks plausible either way so the error goes undetected.
What to do instead
Adopt a fixed written template for every per-unit problem: state S_base, V_base at each voltage level, then Z_base = V_base^2 / S_base, then convert each element with Z_pu,new = Z_pu,old * (S_new/S_old) * (V_old/V_new)^2. Do ten mixed problems with the template until the base-change step is automatic.
The candidate solves a circuit problem by the first method that comes to mind (nodal analysis on a bridge, mesh analysis on a circuit with a current source in the shared branch) and burns eight to ten minutes on algebra instead of switching to superposition, Thevenin, or a source transformation.
Coursework rewards grinding one technique to completion, so candidates commit to a method before scanning the topology; the exam's time budget (roughly three minutes per question average) makes a wrong method choice fatal even when the physics is understood.
What to do instead
Before writing equations, spend fifteen seconds classifying the circuit: count nodes versus meshes, note current sources, dependent sources, and whether only one element's response is asked. Practice a drill where the same circuit is solved three ways and you time each, so you learn which topology favors which method.
On digital logic and state-machine questions, the candidate derives a next-state or output expression from the schematic by inspection and does not verify it against a truth table, so a single missed inverted input or an active-low enable flips the answer.
Boolean simplification by eye is fast and usually right, which trains overconfidence; active-low signals and enable pins are the exact places where inspection fails, and the candidate has no independent check.
What to do instead
For any combinational or sequential block, write the truth table or state table first, then read the answer off the table. For sequential logic, explicitly list present state, input, next state, output for each row before choosing an option.
The candidate answers a motor question using the nameplate full-load current and horsepower directly, skipping the distinction between input power, output mechanical power, and efficiency, and ignoring service factor and the 125% conductor sizing rule.
Motor problems look like simple P = VI arithmetic, so candidates plug nameplate values into the wrong side of the efficiency equation; the National Electrical Code sizing multipliers are learned as trivia rather than as a workflow.
What to do instead
Use a fixed chain for every motor problem: output horsepower to watts, divide by efficiency to get input power, then compute current from voltage and power factor, then apply the applicable 125% or 430% multiplier for the question asked. Practice separating 'what the motor delivers' from 'what the feeder must carry'.
On electronics questions involving diodes, transistors, or op-amps, the candidate assumes an ideal device and ignores the region of operation, so a BJT assumed in forward-active is actually saturated or an op-amp output is driven past its rail.
Ideal-device assumptions are taught first and stick; checking the region of operation requires a second pass that candidates skip when they get a clean number from the ideal model.
What to do instead
Always finish with a consistency check: for a BJT confirm V_CE > 0.2 V (or the stated saturation voltage) and V_BE forward biased; for an op-amp confirm the required output lies within the supply rails; for a diode confirm the assumed on/off state matches the resulting current direction. Make the check a written step, not a mental one.
The candidate treats a control-systems question as pure algebra, computing a transfer function or steady-state error without checking stability, or reading a Bode plot's gain margin and phase margin off the wrong crossover frequency.
Laplace manipulation feels like the whole task, so stability criteria and margin definitions are treated as optional; gain margin is measured at the phase crossover and phase margin at the gain crossover, and candidates routinely swap them.
What to do instead
For every control problem, state which crossover you are using before reading a value: gain margin at the frequency where phase is -180 degrees, phase margin at the frequency where magnitude is 0 dB. Confirm stability with a Routh-Hurwitz check or by counting right-half-plane poles when a closed-loop transfer function is given.
On power-system protection and fault questions, the candidate computes fault current without establishing the system impedance path (transformer, line, source) in per unit, or picks a protective device setting without checking coordination with the upstream device.
Fault analysis is often studied as a formula (I = V/Z) divorced from the one-line diagram, and coordination is studied as a definition rather than as a time-current curve exercise, so the candidate never builds the habit of tracing the path.
What to do instead
Redraw the one-line diagram for every fault problem, mark each impedance in per unit on a common base, and reduce series and parallel combinations explicitly. For coordination questions, sketch the time-current curves and verify the downstream device clears before the upstream device trips at the fault current.
On computer-engineering questions about memory hierarchy, pipelining, or instruction timing, the candidate computes average access time or speedup using only the hit ratio and hit time, omitting the miss penalty, or applies the pipeline speedup formula without accounting for stalls and the fill/drain overhead.
The simplified formulas are memorable and produce a number quickly; the full expressions require an extra term that is easy to drop, and no sanity check reveals the omission.
What to do instead
Write the full expression before substituting: average access time = hit time + miss rate x miss penalty; pipeline speedup = number of stages / (1 + stall cycles per instruction). Then ask whether the answer is bounded sensibly (speedup cannot exceed the number of stages; average access time cannot be below hit time).
The candidate spends disproportionate time on one hard question, then rushes the remaining questions and makes transcription errors on answers already solved on scratch paper.
The exam is scored on total correct answers with no penalty for guessing, but candidates carry over a habit from graded coursework of needing to finish every problem, so they sacrifice many easy points to chase one hard one.
What to do instead
Set a hard per-question cap (about three minutes) in practice, flag and move on when it is hit, and reserve the final fifteen minutes for flagged items and for transferring answers carefully. Simulate this with full-length timed practice exams so the flag-and-return habit is trained, not improvised.