FE Electrical & Computer key terms

A two-terminal linear circuit reduced to one voltage source in series with one resistance, where the source is the open-circuit voltage and the resistance is that seen with sources deactivated. It simplifies load analysis and maximum power transfer calculations.

A two-terminal linear circuit reduced to one current source in parallel with one resistance, where the source is the short-circuit current and the resistance equals the Thevenin resistance. Source conversion links the two forms.

A linear-circuit technique that computes the response to each independent source separately with all others deactivated, then sums the individual responses. It applies only to linear quantities such as voltage and current, not power.

The load receives its greatest possible power when its resistance equals the source resistance seen looking back into the network. Efficiency at that point is only 50 percent, so it is not the same as best operating efficiency.

Setting a load impedance equal to the complex conjugate of the source impedance so that reactive parts cancel and maximum power transfers. In RF work, matching networks also transform impedance to control reflections.

A complex number representing the amplitude and phase of a sinusoid at a single frequency, letting steady-state AC circuits be solved with algebra. Time derivatives become multiplication by j omega.

The ratio of a system output phasor to its input phasor as a function of complex frequency s. Its poles and zeros determine stability, transient response, and frequency response magnitude and phase.

A pair of straight-line approximations showing a transfer function's magnitude in decibels and phase in degrees versus logarithmic frequency. Corner frequencies from poles and zeros set the slopes of each segment.

A logarithmic ratio equal to 20 log of a voltage or current ratio, or 10 log of a power ratio. Cascaded stages add in decibels, and 20 dB corresponds to a factor of ten in amplitude.

A plot of the closed-loop pole locations as one parameter, usually gain, varies from zero to infinity. Branches start at open-loop poles and end at open-loop zeros.

Gain margin is the decibel increase in loop gain that drives the loop to unity at the phase crossover; phase margin is the phase shortfall from 180 degrees at the gain crossover. Both indicate relative stability.

An algebraic test on the coefficients of a characteristic polynomial that counts right-half-plane roots without factoring it. It determines closed-loop stability and the gain range that keeps a system stable.

A diagram in the complex s-plane marking the roots of the denominator (poles) and numerator (zeros) of a transfer function. Pole positions reveal decay rate, oscillation frequency, and stability.

A bandlimited signal can be reconstructed exactly if sampled at more than twice its highest frequency. Sampling below that rate aliases high frequencies onto lower ones, corrupting the recovered signal.

The folding of frequencies above half the sampling rate onto lower apparent frequencies in the sampled spectrum. It is prevented by filtering the analog input before sampling.

An analog low-pass filter placed before a sampler to remove components above the Nyquist frequency. Its transition band and order must be chosen so attenuation is adequate at half the sample rate.

Mapping continuous sample amplitudes onto a finite set of discrete levels. The resulting error is bounded by half a step and produces a noise floor lowered roughly 6 dB per added bit.

A converter that determines each output bit in turn by comparing the input against a trial value from a digital-to-analog converter, from most significant to least. It offers moderate speed at low power.

A buffer and capacitor that capture an input value and hold it steady while a converter digitizes it. It prevents input changes during conversion from corrupting the result.

A grid arrangement of a truth table in Gray-code order so that adjacent cells differ in one variable. Grouping adjacent ones yields a minimized sum-of-products expression.

The rules for manipulating binary variables using AND, OR, and NOT, including De Morgan's laws and distributivity. It provides the algebraic basis for simplifying and proving logic expressions.

An input combination whose output is irrelevant, usually because that combination never occurs. Such entries may be grouped as ones or zeros to simplify logic.

Setup time is how long data must be stable before a clock edge; hold time is how long after. Violations cause metastable flip-flop outputs and unreliable captured data.

A condition in which a flip-flop output hovers between logic levels after a timing violation, resolving unpredictably after a delay. Synchronizers reduce its probability of causing failure.

The difference in arrival times of the same clock edge at different registers. Positive skew can help or hurt setup and hold margins depending on which path it favors.

A sequential logic model with a defined set of states, inputs, outputs, and transition rules. Moore outputs depend only on state; Mealy outputs also depend on current inputs.

A signed binary representation in which the most significant bit carries negative weight, so negation is bitwise inversion plus one. It makes addition and subtraction share one hardware adder.

Temporal locality means recently used data is likely reused soon; spatial locality means nearby addresses are likely accessed. Both justify cache line fetches and replacement policies that improve hit rate.

A condition that prevents the next instruction from issuing in the following cycle. Structural, data, and control hazards are handled by stalls, forwarding, or branch prediction.

An address translation scheme giving each process a private address space mapped to physical frames through page tables. It provides isolation, demand paging, and protection via translation lookaside buffers.

A normalization in which voltages, currents, and impedances are divided by chosen base values, removing transformer turns ratios from calculations. It makes multi-voltage power networks easier to compare and solve.

A method decomposing an unbalanced three-phase set into positive, negative, and zero sequences that are analyzed separately. It underpins fault analysis and relay settings.

Computing currents and voltages during short circuits using sequence networks and impedance data. Results size protective devices and set relay coordination.

A numerical solution of network equations giving bus voltages, angles, and line flows for specified generation and load. Buses are classified as slack, PV, or PQ.

A model placing series winding impedance and shunt magnetizing branch on one side after referring the other side through the turns ratio squared. It predicts regulation, losses, and efficiency.

The cosine of the angle between voltage and current, equal to real power divided by apparent power. Low values increase current and losses for a given real power delivered.

The difference between synchronous speed and rotor speed, expressed as a fraction of synchronous speed. Slip rises with load and determines rotor frequency and developed torque.

The fraction of a switching period during which a switch conducts. In a buck converter, the output voltage approximately equals input times duty cycle in continuous conduction.

A property of circuits obeying superposition and scaling of responses. Linear elements include resistors, capacitors, inductors, and ideal sources; diodes and transistors are nonlinear.