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FE Electrical & Computer practice questions

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Question 1Electrical and Computer: Computer Engineering

In two's-complement arithmetic with 8-bit registers, what is the decimal value of the bit pattern 1111 0110?

  1. -10 Correct answer.
  2. -118
  3. 246
  4. -9

Explanation

The leading bit is 1, so the value is negative. Invert all bits (0000 1001) and add one to get 0000 1010, which is 10, so the value is -10. Equivalently, 1111 0110 = -128 + 64 + 32 + 16 + 4 + 2 = -10.

Question 2Electrical and Computer: Computer Engineering

How many select (control) lines does a 32-to-1 multiplexer require?

  1. 4
  2. 5 Correct answer.
  3. 32
  4. 6

Explanation

An N-to-1 multiplexer needs ceil(log2 N) select lines because the select code must uniquely address each of the N data inputs. For N = 32, log2(32) = 5 select lines.

Question 3Electrical and Computer: Computer Engineering

A 4-bit ripple-carry adder is built from four full adders. What is its main performance limitation compared with a carry-lookahead adder?

  1. It cannot add two's-complement negative numbers correctly.
  2. It consumes more static power because it uses more transistors than a lookahead adder.
  3. It requires a clock signal to sequence the carry between stages.
  4. The carry must propagate serially through each stage, so the worst-case delay grows with the number of bits. Correct answer.

Explanation

In a ripple-carry adder each full adder must wait for the carry-out of the previous stage, so the critical path delay scales linearly with bit width. Carry-lookahead logic computes group generate and propagate signals to shorten that path. A ripple adder is combinational and handles two's-complement operands correctly.

Question 4Electrical and Computer: Computer Engineering

Which statement describes a key property of SRAM cells used in CPU register files and caches?

  1. They retain data without power because they use floating-gate transistors.
  2. They are programmed once at manufacture and cannot be rewritten.
  3. They store a bit as a cross-coupled latch that holds state as long as power is applied. Correct answer.
  4. They store a bit as charge on a capacitor that must be periodically refreshed.

Explanation

An SRAM bit cell is a bistable latch, typically six transistors, that holds its state statically while powered. Because the state is actively latched, no refresh is required, which makes SRAM fast but area-expensive compared with DRAM.

Question 5Electrical and Computer: Computer Engineering

In the IEEE 754 single-precision format, how many bits are allocated to the exponent and to the fraction (significand) field?

  1. 7 exponent bits and 24 fraction bits
  2. 8 exponent bits and 24 fraction bits
  3. 11 exponent bits and 52 fraction bits
  4. 8 exponent bits and 23 fraction bits Correct answer.

Explanation

Single precision uses 1 sign bit, 8 exponent bits with a bias of 127, and 23 stored fraction bits. An implicit leading 1 adds one bit of effective precision, giving 24 significant bits total.

Question 6Electrical and Computer: Computer Engineering

What is the primary purpose of a cache memory in a computer system?

  1. To increase the total addressable memory space beyond the physical RAM size.
  2. To provide nonvolatile backup of main memory contents during power loss.
  3. To reduce the average time to access data by keeping recently used blocks close to the processor. Correct answer.
  4. To translate virtual addresses into physical addresses.

Explanation

Caches exploit temporal and spatial locality by holding recently referenced blocks in fast memory near the CPU, lowering average access latency. They are volatile and do not extend address space or perform address translation.

Question 7Electrical and Computer: Computer Engineering

Which protocol is most appropriate for connecting low-speed sensors on a shared two-wire bus where multiple devices are addressed by unique IDs?

  1. I2C Correct answer.
  2. USB
  3. PCIe
  4. SPI

Explanation

I2C uses two wires, SDA and SCL, with a clocked serial protocol and 7- or 10-bit device addressing, which suits many low-speed sensors sharing one bus. SPI needs separate chip-select lines per device, and PCIe and USB are higher-speed interfaces with more complex protocols.

Question 8Electrical and Computer: Computer Engineering

In a finite state machine, what distinguishes a Moore machine from a Mealy machine?

  1. Moore machines are asynchronous, while Mealy machines are synchronous.
  2. Moore machines have no state register, while Mealy machines do.
  3. Moore outputs depend on the current inputs only, while Mealy outputs depend on state only.
  4. Moore outputs depend only on the current state, while Mealy outputs depend on the current state and inputs. Correct answer.

Explanation

A Moore machine derives its outputs solely from the registered state, so outputs change only on state transitions. A Mealy machine combines current state and current inputs to form outputs, which can respond in the same cycle but may glitch.

Question 9Electrical and Computer: Computer Engineering

A synchronous counter is clocked at 50 MHz and has a terminal count of 249 (counts 0 through 249). What is the frequency of the terminal-count pulse?

  1. 250 kHz
  2. 2 MHz
  3. 200 kHz Correct answer.
  4. 500 kHz

Explanation

The counter has 250 states, so a terminal-count pulse occurs once every 250 clock cycles. The pulse frequency is 50 MHz / 250 = 200 kHz.

Question 10Electrical and Computer: Computer Engineering

A 4-bit synchronous binary counter using T flip-flops is at state 1011. What is the next state after one clock edge?

  1. 1100 Correct answer.
  2. 1010
  3. 1101
  4. 0100

Explanation

The binary value 1011 equals 11, so the next count is 12, which is 1100 in four bits. In a T flip-flop counter, the LSB toggles every cycle and each higher bit toggles when all lower bits are 1, which matches this increment.

Question 11Electrical and Computer: Computer Engineering

A direct-mapped cache has 256 lines and a block size of 16 bytes. To which cache line does the byte address 0x0A3C map?

  1. Line 163 with block offset 12
  2. Line 60
  3. Line 163 Correct answer.
  4. Line 43

Explanation

The block offset uses log2(16) = 4 bits, so the block number is 0x0A3C >> 4 = 0xA3 = 163. With 256 lines, the line index is 163 mod 256 = 163. The offset within the block is 0x0A3C & 0xF = 12, but the question asks for the line.

Question 12Electrical and Computer: Computer Engineering

A direct-mapped cache has a hit time of 1 cycle and a miss penalty of 50 cycles. If the miss rate is 4%, what is the average memory access time?

  1. 51 cycles
  2. 2 cycles
  3. 2.5 cycles
  4. 3 cycles Correct answer.

Explanation

Average access time equals hit time plus miss rate times miss penalty: 1 + 0.04 x 50 = 1 + 2 = 3 cycles. This standard formula weights the full miss penalty by the fraction of accesses that miss.

Question 13Electrical and Computer: Computer Engineering

A pipeline has five stages with stage delays of 2 ns, 3 ns, 2 ns, 4 ns, and 2 ns. Ignoring register overhead, what is the steady-state throughput of the pipeline?

  1. One instruction every 2.6 ns
  2. One instruction every 13 ns
  3. One instruction every 2 ns
  4. One instruction every 4 ns Correct answer.

Explanation

In steady state the clock period is set by the slowest stage, which is 4 ns here, so one instruction completes per 4 ns. The sum of stage delays (13 ns) is the non-pipelined latency, not the throughput period.

Question 14Electrical and Computer: Computer Engineering

A 16-bit ADC has a full-scale input range of 5 V. What is the approximate resolution (LSB size) in volts?

  1. 38 microvolts
  2. 305 microvolts
  3. 76 microvolts Correct answer.
  4. 5 millivolts

Explanation

The LSB size equals full-scale range divided by 2^16 - 1, the number of steps. That is 5 V / 65535, which is about 76 microvolts.

Question 15Electrical and Computer: Computer Engineering

A synchronous sequential circuit uses a single clock and positive-edge-triggered flip-flops. Which condition must hold for reliable operation?

  1. All flip-flops must have identical propagation delays to avoid race conditions.
  2. Input data must be stable for the setup time before the clock edge and the hold time after it. Correct answer.
  3. The clock frequency must be below the combinational logic delay of the longest path.
  4. The clock must have a duty cycle of exactly 50% for the flip-flops to toggle.

Explanation

Setup and hold windows around the active clock edge guarantee that the flip-flop samples a stable value. Violating either window risks metastability or incorrect data capture. Duty cycle and matched delays are not strict requirements for correct edge-triggered operation.

Question 16Electrical and Computer: Computer Engineering

A Mealy FSM detects the overlapping sequence 101 on a serial input. The machine is in the state representing a detected prefix '10' and the next input bit is 1. What output is produced and what is the appropriate next state?

  1. Output 1 and return to the start state, since the trailing 1 can begin a new 101. Correct answer.
  2. Output 1 and go to a state meaning '10' again.
  3. Output 1 and go to a state meaning '11'.
  4. Output 0 and return to the start state.

Explanation

Seeing 1 after prefix '10' completes 101, so a Mealy machine asserts the output in that transition. For overlapping detection, the final 1 also serves as the first bit of a possible new match, so the machine returns to the start state.

Question 17Electrical and Computer: Computer Engineering

A byte-addressable memory has 20 address lines. What is its total addressable capacity?

  1. 512 KiB
  2. 2 MiB
  3. 1 MB as 10^6 bytes exactly
  4. 1 MiB Correct answer.

Explanation

Twenty address lines select 2^20 = 1,048,576 distinct byte locations, which is 1 MiB. The distinction from 10^6 bytes matters because memory capacity uses powers of two.

Question 18Electrical and Computer: Computer Engineering

A processor executes a program with 2 x 10^6 instructions. The instruction mix requires an average of 3.5 cycles per instruction, and the clock is 1 GHz. What is the execution time?

  1. 3.5 ms
  2. 2 ms
  3. 14 ms
  4. 7 ms Correct answer.

Explanation

Total cycles equal instructions times cycles per instruction: 2 x 10^6 x 3.5 = 7 x 10^6 cycles. At 1 GHz, each cycle is 1 ns, so the time is 7 x 10^6 ns, which is 7 ms.

Question 19Electrical and Computer: Computer Engineering

A cache uses LRU replacement and a set contains four ways with recency order A (most recent), B, C, D (least recent). A miss occurs and the new block is placed in the set. Which block is evicted, and what is the new recency order?

  1. A is evicted; the new block becomes most recent, giving order New, B, C, D.
  2. D is evicted; the new block becomes most recent, giving order New, A, B, C. Correct answer.
  3. B is evicted; the new block becomes most recent, giving order New, A, C, D.
  4. D is evicted; the new block becomes least recent, giving order A, B, C, New.

Explanation

LRU evicts the least recently used block, which is D in this set. The newly filled block is the most recently used, so it moves to the front and the others shift down, yielding New, A, B, C.

Question 20Electrical and Computer: Computer Engineering

A 4-bit DAC has a full-scale output of 15 V and a binary input of 1001. Assuming an ideal weighted-resistor DAC with LSB = 1 V, what is the output voltage?

  1. 8 V
  2. 15 V
  3. 10 V
  4. 9 V Correct answer.

Explanation

The input 1001 equals decimal 9, and with an LSB of 1 V the output is 9 V. The weighted-resistor network sums binary-weighted currents, so the output is proportional to the integer code.

Question 21Electrical and Computer: Computer Engineering

In a three-stage pipeline with no forwarding, an ALU result is needed by the immediately following instruction. How many stall cycles are typically inserted, and why?

  1. Zero cycles, because the register file writes and reads in the same cycle.
  2. Three cycles, because every pipeline stage must drain completely.
  3. Two cycles, because the result is not written until the end of the third stage and must be read after that. Correct answer.
  4. One cycle, because only the execute stage must complete.

Explanation

Without forwarding, a producer's result is available only after the write-back stage, while the consumer needs it in its decode/read stage. For a three-stage pipe where execute is stage 2 and write-back is stage 3, two stall cycles are inserted so the consumer reads the updated register.

Question 22Electrical and Computer: Computer Engineering

A synchronous design has a clock period of 10 ns, flip-flop clock-to-Q delay of 1 ns, combinational logic delay of 6 ns, setup time of 1 ns, and clock skew of 1 ns (capture clock arrives later). Does the path meet setup timing, and what is the slack?

  1. Yes; the slack is 1 ns, since required time is 10 + 1 and arrival is 1 + 6 + 1. Correct answer.
  2. Yes; the slack is 2 ns, since skew is ignored in setup analysis.
  3. No; the slack is -1 ns because skew reduces the available time.
  4. Yes; the slack is 3 ns, since only the logic delay matters.

Explanation

With capture clock arriving 1 ns later, the required time at the capture flop is 10 + 1 = 11 ns. The data arrival is clock-to-Q plus logic plus setup, 1 + 6 + 1 = 8 ns, so the slack is 11 - 8 = 3 ns. Note that positive capture-side skew increases the setup margin.

Question 23Electrical and Computer: Computer Engineering

A CPU uses a two-level cache hierarchy. L1 hit time is 1 cycle with a 10% miss rate; L2 hit time is 10 cycles with a 20% local miss rate; main memory access takes 100 cycles. What is the average memory access time?

  1. 3 cycles
  2. 12 cycles
  3. 4 cycles Correct answer.
  4. 11 cycles

Explanation

AMAT = L1 hit time + L1 miss rate x (L2 hit time + L2 miss rate x memory penalty) = 1 + 0.10 x (10 + 0.20 x 100) = 1 + 0.10 x 30 = 4 cycles.

Question 24Electrical and Computer: Computer Engineering

An FSM must detect the overlapping pattern 1101 on a serial input. After observing the prefix 110, the next input bit is 1. What is the correct next state for overlapping detection?

  1. A state representing the suffix '1'.
  2. A state representing the suffix '01'.
  3. A state representing the suffix '11'. Correct answer.
  4. A state representing the suffix '1101'.

Explanation

The observed stream ends in 1101, which completes the pattern, but for overlapping detection the machine must also retain the longest suffix that is a prefix of 1101. The suffix '11' is such a prefix, so the machine moves to that state.

Question 25Electrical and Computer: Computer Engineering

A 32-bit processor has a 4-way set-associative L1 cache with 64 KiB capacity and 64-byte blocks. How many sets does the cache contain?

  1. 64
  2. 256 Correct answer.
  3. 1024
  4. 4096

Explanation

The cache holds 64 KiB / 64 B = 1024 blocks. With 4 ways per set, the number of sets is 1024 / 4 = 256, and the set index uses log2(256) = 8 bits.

Question 26Electrical and Computer: Computer Engineering

In the IEEE 754 single-precision format, how many bits are allocated to the exponent field?

  1. 8 Correct answer.
  2. 7
  3. 10
  4. 11

Explanation

Single precision uses 1 sign bit, 8 exponent bits, and 23 fraction bits for a total of 32 bits. The exponent is stored in biased form with a bias of 127.

Question 27Electrical and Computer: Computer Engineering

Which logic gate family output is produced by the Boolean expression A'B + AB'?

  1. Exclusive-NOR
  2. Exclusive-OR Correct answer.
  3. NOR
  4. NAND

Explanation

The expression A'B + AB' is the canonical sum-of-products form of the XOR function, which is true when exactly one input is true. XNOR would add the AB and A'B' terms.

Question 28Electrical and Computer: Computer Engineering

A two-input AND gate drives a two-input OR gate, whose other input is C. Which expression describes the OR gate output?

  1. A + BC
  2. ABC
  3. AB + C Correct answer.
  4. (A + B)C

Explanation

The AND gate produces AB, and the OR gate combines that with C to yield AB + C. Operator precedence in Boolean algebra places AND before OR.

Question 29Electrical and Computer: Computer Engineering

In the context of computer architecture, what does the term 'von Neumann bottleneck' refer to?

  1. The delay introduced by the clock distribution network
  2. The limited bandwidth of the path between processor and memory Correct answer.
  3. The limited number of general-purpose registers
  4. The latency of the arithmetic logic unit

Explanation

In a von Neumann machine, instructions and data share a single memory path, so the processor can be starved waiting for memory. This throughput limitation is what the term names.

Question 30Electrical and Computer: Computer Engineering

Which number system representation stores the negative of a value by inverting every bit and adding one?

  1. Sign-magnitude
  2. Two's complement Correct answer.
  3. One's complement
  4. Excess-127 (biased)

Explanation

Two's complement negation is defined as the bitwise complement plus one, which gives a single representation for zero and a clean arithmetic range. One's complement only inverts the bits.

Question 31Electrical and Computer: Computer Engineering

Which memory type loses its stored contents when power is removed but offers the highest density and lowest cost per bit?

  1. Dynamic RAM Correct answer.
  2. Static RAM
  3. Flash memory
  4. Ferroelectric RAM

Explanation

DRAM stores each bit as charge on a capacitor, so it is volatile but very dense and inexpensive, which makes it the standard main memory technology. SRAM uses more transistors per bit and is costlier.

Question 32Electrical and Computer: Computer Engineering

Which addressing mode computes the effective address as the sum of a base register and a constant offset encoded in the instruction?

  1. Immediate
  2. PC-relative
  3. Register indirect
  4. Base-plus-displacement Correct answer.

Explanation

Base-plus-displacement adds a signed constant in the instruction to the contents of a base register to form the effective address. This supports array and structure access.

Question 33Electrical and Computer: Computer Engineering

A signal is transmitted over a channel that supports four distinct voltage levels. How many bits are carried by each symbol?

  1. 3
  2. 1
  3. 2 Correct answer.
  4. 4

Explanation

With M distinct signaling levels, each symbol conveys log2(M) bits, and log2(4) equals 2. So each symbol carries two bits.

Question 34Electrical and Computer: Computer Engineering

Which logic gate produces a HIGH output only when all of its inputs are HIGH?

  1. OR
  2. AND Correct answer.
  3. NOR
  4. XOR

Explanation

An AND gate outputs 1 only for the all-ones input combination, which is the definition of the AND function. Every other input pattern yields 0.

Question 35Electrical and Computer: Computer Engineering

A 16-bit register holds the value 0x00F0. What does this value represent in unsigned decimal?

  1. 240 Correct answer.
  2. 15
  3. 1920
  4. 255

Explanation

0x00F0 equals 15 times 16, because the hex digit F occupies the sixteens place. That product is 240.

Question 36Electrical and Computer: Computer Engineering

A Karnaugh map for a four-variable function has the minterms 0, 1, 2, 3, 8, 9, 10, and 11. Which simplified sum-of-products expression results?

  1. B' Correct answer.
  2. A'
  3. C'
  4. D'

Explanation

The listed minterms cover all cells where B equals 0, regardless of A, C, and D, so the function simplifies to B'. The two groups of four merge into one group of eight.

Question 37Electrical and Computer: Computer Engineering

An 8-bit two's complement register contains 0b11110110. What signed decimal value does it hold?

  1. 246
  2. -11
  3. -10 Correct answer.
  4. -9

Explanation

The leading bit is 1, so the value is negative. Inverting the bits gives 0b00001001 and adding one gives 0b00001010, which is 10, so the value is -10.

Question 38Electrical and Computer: Computer Engineering

A combinational circuit has three inputs and produces a 1 only when an odd number of inputs are 1. Which single gate implements this function?

  1. Three-input OR
  2. Three-input XOR Correct answer.
  3. Three-input NAND
  4. Three-input XNOR

Explanation

The XOR function is 1 when an odd number of its inputs are 1, and this property extends directly to the three-input case. The truth table has four minterms with ones.

Question 39Electrical and Computer: Computer Engineering

A JK flip-flop has J and K both tied HIGH and is clocked. What behavior does it exhibit?

  1. It toggles on each active clock edge Correct answer.
  2. It holds its current state
  3. It sets to 1 and stays there
  4. It resets to 0 and stays there

Explanation

With both J and K asserted, the JK flip-flop enters toggle mode and complements its output at each active edge. This is the basis for building ripple and synchronous counters.

Question 40Electrical and Computer: Computer Engineering

A synchronous circuit must count from 0 through 5 repeatedly. What is the minimum number of flip-flops required?

  1. 3 Correct answer.
  2. 2
  3. 6
  4. 4

Explanation

Six states require a state encoding with at least six codes, and two flip-flops provide only four. Three flip-flops provide eight codes, which is the smallest sufficient number.

Question 41Electrical and Computer: Computer Engineering

An instruction pipeline suffers a branch penalty of 3 cycles and executes 20% branch instructions with a 40% taken rate. What is the average cycles-per-instruction penalty from branches alone?

  1. 0.80
  2. 0.60
  3. 0.24 Correct answer.
  4. 0.12

Explanation

The penalty per instruction equals branch frequency times taken rate times penalty cycles: 0.20 x 0.40 x 3 = 0.24. This adds to the base CPI.

Question 42Electrical and Computer: Computer Engineering

A system uses Hamming code with 4 data bits. How many parity bits are needed to correct a single-bit error?

  1. 4
  2. 2
  3. 3 Correct answer.
  4. 5

Explanation

The Hamming condition requires 2^p >= m + p + 1, where m is 4. With p equal to 3, 8 >= 8 holds, so three parity bits suffice.

Question 43Electrical and Computer: Computer Engineering

Which statement correctly distinguishes a microprocessor from a microcontroller?

  1. A microcontroller cannot execute stored programs
  2. A microcontroller integrates CPU, memory, and peripherals on one chip Correct answer.
  3. A microprocessor is restricted to embedded control tasks
  4. A microprocessor always contains on-chip flash program memory

Explanation

A microcontroller is a complete system on a chip that includes the CPU along with RAM, nonvolatile program memory, and peripherals such as timers and serial ports. A microprocessor is typically just the CPU and needs external support chips.

Question 44Electrical and Computer: Computer Engineering

A memory system uses even parity. The byte 0b10110101 is transmitted. What is the correct parity bit?

  1. 2
  2. It cannot be determined
  3. 1 Correct answer.
  4. 0

Explanation

The byte contains five 1s, which is an odd count. Even parity requires the total number of 1s including the parity bit to be even, so the parity bit must be 1.

Question 45Electrical and Computer: Computer Engineering

A CPU has a 2 GHz clock and executes a program in 5 x 10^8 cycles. What is the execution time?

  1. 2.5 s
  2. 0.10 s
  3. 0.25 s Correct answer.
  4. 0.50 s

Explanation

Execution time equals cycles divided by clock frequency: 5 x 10^8 divided by 2 x 10^9 equals 0.25 seconds. The clock period is 0.5 ns.

Question 46Electrical and Computer: Computer Engineering

Which statement about a set-associative cache is correct when the associativity is increased while capacity and block size stay fixed?

  1. The hit time always decreases
  2. The number of sets decreases and conflict misses tend to fall Correct answer.
  3. The number of sets increases and conflict misses tend to rise
  4. The block size increases proportionally

Explanation

With fixed capacity and block size, raising associativity means fewer sets but more ways per set, so fewer blocks compete for the same set. This reduces conflict misses at the cost of more comparators and possibly longer hit time.

Question 47Electrical and Computer: Computer Engineering

A 4-bit ripple-carry adder adds 0b0111 and 0b0001. What are the 4-bit sum and the carry-out?

  1. Sum 1111, carry-out 0
  2. Sum 0110, carry-out 1
  3. Sum 1000, carry-out 1
  4. Sum 1000, carry-out 0 Correct answer.

Explanation

Seven plus one equals eight, which is 0b1000 in four bits, so the sum fits with no carry out of the most significant position. The carry propagates through all four stages but leaves the final sum bit at 1.

Question 48Electrical and Computer: Computer Engineering

A 32-bit processor uses 4-byte instructions and a byte-addressable memory. If the program counter holds 0x00001004 and the instruction uses PC-relative addressing with an offset of -4, what is the target address?

  1. 0x00001008
  2. 0x00001004
  3. 0x00001000 Correct answer.
  4. 0x00000FFC

Explanation

PC-relative addressing adds the offset to the program counter value, giving 0x00001004 plus (-4) equals 0x00001000. Whether the updated PC is used depends on the architecture, but here the stated PC is the base.

Question 49Electrical and Computer: Computer Engineering

A direct-mapped cache with 16 lines and 8-byte blocks receives the byte address 0x00C8. Which line does it map to?

  1. 25
  2. 8
  3. 12
  4. 9 Correct answer.

Explanation

The block number equals the address divided by the block size: 200 divided by 8 equals 25. The line index is the block number modulo the number of lines, so 25 modulo 16 equals 9.

Question 50Electrical and Computer: Computer Engineering

A sequential circuit has a setup time of 2 ns, a clock-to-Q delay of 1 ns, and a maximum combinational delay of 5 ns. What is the minimum clock period?

  1. 6 ns
  2. 7 ns
  3. 8 ns Correct answer.
  4. 9 ns

Explanation

The minimum period must satisfy the setup constraint: clock-to-Q plus combinational delay plus setup time, which is 1 + 5 + 2 = 8 ns. Any shorter period would violate the setup requirement.