Electrical and Computer: Computer Engineering
The computer engineering domain of the FE Electrical and Computer exam tests digital design and computer organization as one timing-and-abstraction problem. Questions move from number systems and Boolean algebra to sequential machines, instruction execution, pipelining, and the memory hierarchy. The exam rewards candidates who can connect a truth table to a gate-level implementation and then to a clock-period or performance constraint.
Digital logic and timing
- Convert signed values with two’s complement: an n-bit word spans −2^(n−1) to 2^(n−1)−1. Overflow occurs when the carry into and the carry out of the sign bit differ.
- Reduce combinational logic with Boolean identities or Karnaugh maps, then check for static-1 and static-0 hazards when the output feeds an asynchronous input.
- For a synchronous register-to-register path, the minimum clock period is t_cq + t_comb + t_setup + t_skew; hold time is checked on the shortest path, not the longest.
- A finite-state machine needs a state diagram, state encoding, next-state logic, and output logic. Moore outputs depend only on state; Mealy outputs can change with inputs between clock edges.
Architecture and memory
- Average memory access time is AMAT = hit time + miss rate × miss penalty. Split or multilevel caches change both terms, so do not combine them without tracking which level is being described.
- Pipeline speedup is limited by the longest stage plus register overhead; data, control, and structural hazards require forwarding, stalling, or scheduling.
- Cache index, tag, and offset fields come from the address width. Byte offset = log2(block size in bytes), index = log2(number of sets), and tag = remaining bits.
Worked example
A register-to-register datapath has t_cq = 0.12 ns, t_comb = 1.65 ns, t_setup = 0.18 ns, and clock skew = 0.05 ns. Find the maximum clock frequency. The required period is T = 0.12 + 1.65 + 0.18 + 0.05 = 2.00 ns, so f_max = 1/2.00 ns = 500 MHz. Skew is added because the receiving register’s clock arrives late relative to the launching register in this conservative check.
Traps that cost marks
- Mixing nanoseconds and picoseconds, or treating MHz as 10^6 Hz but then using 10^9 in the denominator.
- Forgetting that hold-time checks use the minimum delay path and can fail even when setup passes.
- Confusing hit rate with miss rate, or applying a miss penalty to every access instead of only misses.
- Using a byte address directly as a word address when indexing a word-addressed cache.
- Ignoring pipeline register setup/hold overhead when computing ideal speedup.